公开(公告)号：US4782250A

公开(公告)日：1988-11-01

申请号：US91565

申请日：1987-08-31

申请人： Robert D. Adams ,  Roy C. Flaker ,  Kenneth S. Gray ,  Howard L. Kalter

发明人： Robert D. Adams ,  Roy C. Flaker ,  Kenneth S. Gray ,  Howard L. Kalter

IPC分类号： H03K17/08 ,  H03K19/003 ,  H03K19/017 ,  H03K19/0185 ,  H03K19/094 ,  H03K19/0948 ,  H03K17/04 ,  H03K17/687 ,  H03K19/096

CPC分类号： H03K19/0948 ,  H03K19/00315 ,  H03K19/01721 ,  H03K19/09429

摘要： A CMOS off-chip driver circuit is provided which includes a first P-channel field effect transistor arranged in series with a second or pull-up P-channel transistor and a third P-channel transistor connected from the common point between the first and second transistors and the gate electrode of the first transistor. The first and second transistors are disposed between a data output terminal and a first voltage source having a supply voltage of a given magnitude, with the data output terminal also being connected to a circuit or system including a second voltage source having a supply voltage of a magnitude significantly greater than that of the given magnitude. In a more specific aspect of this invention, a fourth P-channel transistor, disposed in a common N-well with the other P-channel transistors, is connected at its source to the first voltage source and at its drain to the common N-well, with its gate electrode being connected to the data output terminal.

公开(公告)号：US5563086A

公开(公告)日：1996-10-08

申请号：US406284

申请日：1995-03-17

申请人： Claude L. Bertin ,  Wayne J. Howell ,  Erik L. Hedberg ,  Howard L. Kalter ,  Gordon A. Kelley, Jr.

发明人： Claude L. Bertin ,  Wayne J. Howell ,  Erik L. Hedberg ,  Howard L. Kalter ,  Gordon A. Kelley, Jr.

IPC分类号： G11C5/00 ,  H01L25/065 ,  H01L21/70

CPC分类号： H01L25/0657 ,  G11C5/06 ,  H01L2224/48091 ,  H01L2225/0651 ,  H01L2225/06551 ,  H01L2225/06555 ,  H01L2225/06572 ,  H01L2225/06596 ,  H01L2924/10253

摘要： An integrated memory cube structure and method of fabrication wherein stacked semiconductor memory chips are integrated by a controlling logic chip such that a more powerful memory architecture is defined with the functional appearance of a single, higher level memory chip. A memory/logic cube is formed having N memory chips and at least one logic chip, with each memory chip of the cube having M memory devices. The controlling logic chip coordinates external communication with the N memory chips such that a single memory chip architecture with N.times.M memory devices appears at the cube's I/O pins. A corresponding fabrication technique includes an approach for facilitating metallization patterning on the side surface of the memory subunit.

摘要翻译： 一种集成的存储立方体结构和制造方法，其中堆叠的半导体存储器芯片由控制逻辑芯片集成，使得更强大的存储器架构被定义为单个更高级存储器芯片的功能外观。 形成具有N个存储器芯片和至少一个逻辑芯片的存储器/逻辑立方体，其中立方体的每个存储器芯片具有M个存储器件。 控制逻辑芯片协调与N个存储器芯片的外部通信，使得具有NxM存储器件的单个存储器芯片架构出现在立方体的I / O引脚处。 相应的制造技术包括用于在存储器子单元的侧表面上促进金属化图案化的方法。

公开(公告)号：US4603341A

公开(公告)日：1986-07-29

申请号：US530452

申请日：1983-09-08

申请人： Claude L. Bertin ,  Howard L. Kalter

发明人： Claude L. Bertin ,  Howard L. Kalter

IPC分类号： G11C17/08 ,  H01L21/822 ,  H01L21/8246 ,  H01L27/00 ,  H01L27/06 ,  H01L27/10 ,  H01L27/112 ,  H01L29/78 ,  G11C17/00

CPC分类号： H01L27/11519 ,  H01L21/8221 ,  H01L27/0688 ,  H01L27/112

摘要： A read only memory array of stacked IGFET devices composed of first and second sub-arrays of field effect transistors. The first sub-array of first field effect transistors is formed in a substrate. Each of the first field effect transistor devices is responsive to a polysilicon gate electrode. The second sub-array of second field effect transistors is formed in a layer of laser annealed polysilicon material which overlies the first sub-array. The gate electrodes of the first field effect transistors act as the gate electrodes of the second field effect transistors.

摘要翻译： 由场效应晶体管的第一和第二子阵列组成的堆叠IGFET器件的只读存储器阵列。 第一场效应晶体管的第一子阵列形成在衬底中。 第一场效应晶体管器件中的每一个都响应于多晶硅栅电极。 第二场效应晶体管的第二子阵列形成在覆盖在第一子阵列上的激光退火多晶硅材料层中。 第一场效应晶体管的栅电极用作第二场效应晶体管的栅电极。

公开(公告)号：US5972745A

公开(公告)日：1999-10-26

申请号：US866674

申请日：1997-05-30

申请人： Howard L. Kalter ,  Edward J. Nowak ,  Xiaowei Tian ,  Minh H. Tong ,  William R. Tonti

发明人： Howard L. Kalter ,  Edward J. Nowak ,  Xiaowei Tian ,  Minh H. Tong ,  William R. Tonti

IPC分类号： H01L21/265 ,  H01L21/761 ,  H01L21/8238

CPC分类号： H01L21/823892 ,  H01L21/761 ,  H01L21/26586

摘要： A method of forming a self-aligned halo-isolated well with a single mask is disclosed. First, a layer of resist is disposed over at least a portion of a substrate's surface. Then, an impurity of a first polarity type is implanted at an angle into the substrate through a gap in the layer of resist, thus forming a well having the impurity of the first polarity, which extends beneath the layer of resist. An impurity of a second polarity type is also implanted, using the same mask as previously used. The second implantation forms a well of the impurity of the second polarity disposed within the well of to impurity of the first polarity.

摘要翻译： 公开了一种用单一掩模形成自对准卤素隔离井的方法。 首先，将抗蚀剂层设置在衬底表面的至少一部分上。 然后，第一极性类型的杂质通过抗蚀剂层中的间隙以一定角度注入到衬底中，从而形成具有在抗蚀剂层下方延伸的具有第一极性杂质的阱。 使用与以前使用的相同的掩模也植入第二极性类型的杂质。 第二次注入形成设置在第一极性杂质的阱内的第二极性杂质的阱。

公开(公告)号：US5814885A

公开(公告)日：1998-09-29

申请号：US848037

申请日：1997-04-28

申请人： H. Bernhard Pogge ,  Johann Greschner ,  Howard L. Kalter

发明人： H. Bernhard Pogge ,  Johann Greschner ,  Howard L. Kalter

IPC分类号： H01L23/13 ,  H01L29/06 ,  H01L29/04 ,  H01L23/06

CPC分类号： H01L24/95 ,  H01L23/13 ,  H01L29/0657 ,  H01L2224/83141 ,  H01L2224/95136 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01023 ,  H01L2924/01027 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/10158 ,  H01L2924/10253 ,  H01L2924/10329 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/3025

摘要： An integrated circuit package including a carrier having a surface topography of projections or recesses for supporting individual semiconductor circuit chips having a conversely matching bottom surface topography to permit self-aligned positioning of the chip on the carrier.

摘要翻译： 一种集成电路封装，包括具有用于支撑具有相反匹配的底表面形貌的各个半导体电路芯片的突起或凹槽的表面形貌的载体，以允许芯片在载体上的自对准定位。

公开(公告)号：US5571754A

公开(公告)日：1996-11-05

申请号：US555738

申请日：1995-11-09

申请人： Claude L. Bertin ,  Wayne J. Howell ,  Howard L. Kalter

发明人： Claude L. Bertin ,  Wayne J. Howell ,  Howard L. Kalter

IPC分类号： H01L23/538 ,  H01L25/065 ,  H01L25/07 ,  H01L25/18 ,  H01L21/60

CPC分类号： H01L25/0657 ,  H01L25/18 ,  H01L2224/24145 ,  H01L2224/32145 ,  H01L2224/48145 ,  H01L2225/06506 ,  H01L2225/06524 ,  H01L2225/06541 ,  H01L2225/06551 ,  H01L2225/06586 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/19041

摘要： An endcap chip is provided for a multichip stack comprising multiple integrated circuit chips laminated together. The endcap chip has a substrate with an upper surface and a edge surface, which extends in a plane orthogonal to the upper surface. At least one conductive, monolithic L-connect is disposed over the substrate such that a first leg extends at least partially over the upper surface of the substrate and a second leg extends at least partially over the edge surface of the substrate. When the endcap chip is located at the end of the multichip stack, the at least one conductive, monolithic L-connect electrically connects metal on an end face of the stack to metal on a side face of the stack. A fabrication process is set forth for producing the endcap chip with lithographically defined dimensions.

摘要翻译： 提供了一种用于多芯片堆叠的端盖芯片，其包括层叠在一起的多个集成电路芯片。 端盖芯片具有上表面和边缘表面的基板，该基板在与上表面正交的平面中延伸。 至少一个导电的单片L形连接器设置在衬底上，使得第一腿部至少部分地延伸到衬底的上表面上，并且第二腿部至少部分地延伸到衬底的边缘表面上。 当端盖芯片位于多芯片堆叠的端部时，至少一个导电的单片L形连接器将堆叠的端面上的金属与堆叠的侧面上的金属电连接。 阐述了用于制造具有光刻尺寸的端盖芯片的制造工艺。

公开(公告)号：US5561622A

公开(公告)日：1996-10-01

申请号：US120993

申请日：1993-09-13

申请人： Claude L. Bertin ,  Wayne J. Howell ,  Erik L. Hedberg ,  Howard L. Kalter ,  Gordon A. Kelley, Jr.

发明人： Claude L. Bertin ,  Wayne J. Howell ,  Erik L. Hedberg ,  Howard L. Kalter ,  Gordon A. Kelley, Jr.

IPC分类号： G11C5/00 ,  H01L25/065 ,  G11C5/06 ,  H01L23/02

CPC分类号： H01L25/0657 ,  G11C5/06 ,  H01L2224/48091 ,  H01L2225/0651 ,  H01L2225/06551 ,  H01L2225/06555 ,  H01L2225/06572 ,  H01L2225/06596 ,  H01L2924/10253

摘要： An integrated memory cube structure and method of fabrication wherein stacked semiconductor memory chips are integrated by a controlling logic chip such that a more powerful memory architecture is defined with the functional appearance of a single, higher level memory chip. A memory/logic cube is formed having N memory chips and at least one logic chip, with each memory chip of the cube having M memory devices. The controlling logic chip coordinates external communication with the N memory chips such that a single memory chip architecture with N.times.M memory devices appears at the cube's I/O pins. A corresponding fabrication technique includes an approach for facilitating metallization patterning on the side surface of the memory subunit.

摘要翻译： 一种集成的存储立方体结构和制造方法，其中堆叠的半导体存储器芯片由控制逻辑芯片集成，使得更强大的存储器架构被定义为单个更高级存储器芯片的功能外观。 形成具有N个存储器芯片和至少一个逻辑芯片的存储器/逻辑立方体，其中立方体的每个存储器芯片具有M个存储器件。 控制逻辑芯片协调与N个存储器芯片的外部通信，使得具有NxM存储器件的单个存储器芯片架构出现在立方体的I / O引脚处。 相应的制造技术包括用于在存储器子单元的侧表面上促进金属化图案化的方法。

公开(公告)号：US5463335A

公开(公告)日：1995-10-31

申请号：US969594

申请日：1992-10-30

申请人： Sridhar Divakaruni ,  Jeffrey H. Dreibelbis ,  Wayne F. Ellis ,  Anatol Furman ,  Howard L. Kalter

发明人： Sridhar Divakaruni ,  Jeffrey H. Dreibelbis ,  Wayne F. Ellis ,  Anatol Furman ,  Howard L. Kalter

IPC分类号： H01L27/00 ,  H03K17/22

CPC分类号： H03K17/223

摘要： A power up detection circuit is provided which includes a power supply terminal, an output terminal, an impedance device coupling the output terminal to the power supply terminal and a latch including a first inverter having a first device connected between the output terminal and a point of reference potential and a second device connected between the output terminal and the power supply terminal, the devices are designed so that subthreshold current passing through the first device is greater than the effective subthreshold current passing through the impedance device and the second device, and a second inverter including third and fourth devices which are designed so that a smaller subthreshold current passes through the third device than the subthreshold current passing through the fourth device. The power up circuit may further include a capacitor connected between the power supply terminal and gate electrodes of the first and second devices.

摘要翻译： 提供了一种上电检测电路，其包括电源端子，输出端子，将输出端子耦合到电源端子的阻抗装置和包括第一反相器的锁存器，第一反相器具有连接在输出端子与点 参考电位和连接在输出端子和电源端子之间的第二器件，器件被设计成使得通过第一器件的亚阈值电流大于通过阻抗器件和第二器件的有效亚阈值电流，并且第二器件 逆变器包括第三和第四器件，其被设计为使得比通过第四器件的亚阈值电流更小的亚阈值电流通过第三器件。 上电电路还可以包括连接在第一和第二器件的电源端子和栅电极之间的电容器。

公开(公告)号：US5399516A

公开(公告)日：1995-03-21

申请号：US930797

申请日：1992-09-21

申请人： Albert S. Bergendahl ,  Claude L. Bertin ,  John E. Cronin ,  Howard L. Kalter ,  Donald M. Kenney ,  Chung H. Lam ,  Hsing-San Lee

发明人： Albert S. Bergendahl ,  Claude L. Bertin ,  John E. Cronin ,  Howard L. Kalter ,  Donald M. Kenney ,  Chung H. Lam ,  Hsing-San Lee

IPC分类号： H01L27/10 ,  H01L21/8239 ,  H01L21/8242 ,  H01L21/8247 ,  H01L27/105 ,  H01L27/108 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  H01L21/308

CPC分类号： H01L29/7882 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/10829 ,  H01L27/115

摘要： A semiconductor device memory array formed on a semiconductor substrate comprising a multiplicity of field effect transistor DRAM devices disposed in array is disclosed. Each of the DRAM devices is paired with a non-volatile EEPROM cell and the EEPROM cells are disposed in a shallow trench in the semiconductor substrate running between the DRAM devices such that each DRAM-EEPROM pair shares a common drain diffusion. The EEPROM cells are arranged in the trench such that there are discontinuous laterally disposed floating gate polysilicon electrodes and continuous horizontally disposed program and recall gate polysilicon electrodes. The floating gate is separated from the program and recall gates by a silicon rich nitride. The array of the invention provides high density shadow RAMs. Also disclosed are methods for the fabrication of devices of the invention.

摘要翻译： 公开了一种形成在半导体衬底上的半导体器件存储器阵列，其包括设置成阵列的多个场效应晶体管DRAM器件。 每个DRAM器件与非易失性EEPROM单元配对，并且EEPROM单元被布置在运行在DRAM器件之间的半导体衬底中的浅沟槽中，使得每个DRAM-EEPROM对共享共同的漏极扩散。 EEPROM单元布置在沟槽中，使得存在不连续的侧向设置的浮栅多晶硅电极和连续的水平布置的程序和调用栅极多晶硅电极。 浮动栅极与程序分离，并通过富含硅的氮化物来调用栅极。 本发明的阵列提供高密度影子RAM。 还公开了用于制造本发明的装置的方法。

公开(公告)号：US4566022A

公开(公告)日：1986-01-21

申请号：US461421

申请日：1983-01-27

申请人： Howard L. Kalter ,  Donald B. Kiley

发明人： Howard L. Kalter ,  Donald B. Kiley

IPC分类号： H01L21/822 ,  H01L21/82 ,  H01L27/04 ,  H01L27/112 ,  H01L27/118 ,  H01L29/78

CPC分类号： H01L27/112

摘要： A transistor array arrangement for providing high-density semiconductor logic circuits in double polysilicon technology is described. Semiconductor, for example, FET, logic circuits have four independent but simultaneously accessible FET devices which are formed by intersecting sets of polysilicon gate lines. The four FET devices share a common first diffusion, for example a source, surrounded by four logically independent second diffusions, for example drains. A three-bit decode device is made which includes this array design.

摘要翻译： 描述了用于在双晶体技术中提供高密度半导体逻辑电路的晶体管阵列布置。 半导体，例如FET，逻辑电路具有四个独立但可同时访问的FET器件，它们由多个多晶硅栅极线的相交组合形成。 四个FET器件共享共同的第一扩散，例如由四个逻辑上独立的第二扩散（例如漏极）包围的源。 制作了一个包含这种阵列设计的三位解码器。