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    Patterned SOI by oxygen implantation and annealing
    3.
    发明授权
    Patterned SOI by oxygen implantation and annealing 有权
    通过氧气注入和退火进行图案化SOI

    公开(公告)号：US07317226B2

    公开(公告)日：2008-01-08

    申请号：US10993270

    申请日：2004-11-19

    申请人： Keith E. Fogel ,  Mark C. Hakey ,  Steven J. Holmes ,  Devendra K. Sadana ,  Ghavam G. Shahidi

    发明人： Keith E. Fogel ,  Mark C. Hakey ,  Steven J. Holmes ,  Devendra K. Sadana ,  Ghavam G. Shahidi

    IPC分类号： H01L27/01

    CPC分类号： H01L21/76243 ,  H01L21/26506 ,  H01L21/76267 ,  Y10T428/12674 ,  Y10T428/12681

    摘要： Methods for forming a patterned SOI region in a Si-containing substrate is provided which has geometries of about 0.25 μm or less. Specifically, one method includes the steps of: forming a patterned dielectric mask on a surface of a Si-containing substrate, wherein the patterned dielectric mask includes vertical edges that define boundaries for at least one opening which exposes a portion of the Si-containing substrate; implanting oxygen ions through the at least one opening removing the mask and forming a Si layer on at least the exposed surfaces of the Si-containing substrate; and annealing at a temperature of about 1250° C. or above and in an oxidizing ambient so as to form at least one discrete buried oxide region in the Si-containing substrate. In one embodiment, the mask is not removed until after the annealing step; and in another embodiment, the Si-containing layer is formed after annealing and mask removal.

    摘要翻译： 提供了在含Si衬底中形成图案化SOI区的方法，其具有约0.25μm或更小的几何形状。 具体而言，一种方法包括以下步骤：在含Si衬底的表面上形成图案化电介质掩模，其中，图案化电介质掩模包括垂直边缘，其限定至少一个露出一部分含Si衬底的开口的边界 ; 通过所述至少一个开口注入氧离子，去除所述掩模并在至少所述含Si衬底的暴露表面上形成Si层; 并在约1250℃或更高的温度下和在氧化环境中进行退火，以便在含Si衬底中形成至少一个离散的掩埋氧化物区域。 在一个实施例中，直到退火步骤之后，掩模才被去除; 并且在另一个实施方案中，在退火和掩模去除之后形成含Si层。

    Formation of silicon-germanium-on-insulator (SGOI) by an integral high temperature SIMOX-Ge interdiffusion anneal
    4.
    发明授权
    Formation of silicon-germanium-on-insulator (SGOI) by an integral high temperature SIMOX-Ge interdiffusion anneal 失效
    通过整体高温SIMOX-Ge相互扩散退火形成绝缘体上硅锗（SGOI）

    公开(公告)号：US07084050B2

    公开(公告)日：2006-08-01

    申请号：US11039602

    申请日：2005-01-19

    申请人： Stephen W. Bedell ,  Joel P. de Souza ,  Keith E. Fogel ,  Devendra K. Sadana ,  Ghavam G. Shahidi

    发明人： Stephen W. Bedell ,  Joel P. de Souza ,  Keith E. Fogel ,  Devendra K. Sadana ,  Ghavam G. Shahidi

    IPC分类号： H01L21/20 ,  H01L21/76 ,  H01L21/31

    CPC分类号： H01L21/76243 ,  H01L21/26506 ,  H01L21/76267 ,  Y10T428/12674 ,  Y10T428/12681

    摘要： A method of forming a substantially relaxed, high-quality SiGe-on-insulator substrate material using SIMOX and Ge interdiffusion is provided. The method includes first implanting ions into a Si-containing substrate to form an implanted-ion rich region in the Si-containing substrate. The implanted-ion rich region has a sufficient ion concentration such that during a subsequent anneal at high temperatures a barrier layer that is resistant to Ge diffusion is formed. Next, a Ge-containing layer is formed on a surface of the Si-containing substrate, and thereafter a heating step is performed at a temperature which permits formation of the barrier layer and interdiffusion of Ge thereby forming a substantially relaxed, single crystal SiGe layer atop the barrier layer.

    摘要翻译： 提供了使用SIMOX和Ge相互扩散形成基本上松弛的，优质的绝缘体上硅衬底材料的方法。 该方法包括首先将离子注入到含Si衬底中以在含Si衬底中形成植入离子富集区。 注入离子富集区具有足够的离子浓度，使得在随后的高温退火期间形成耐Ge扩散的阻挡层。 接下来，在含Si衬底的表面上形成Ge含有层，然后在允许形成阻挡层和Ge的相互扩散的温度下进行加热步骤，从而形成基本上松弛的单晶SiGe层 阻挡层顶部。

    Strained semiconductor-on-insulator by addition and removal of atoms in a semiconductor-on-insulator
    10.
    发明授权
    Strained semiconductor-on-insulator by addition and removal of atoms in a semiconductor-on-insulator 有权
    通过在绝缘体上半导体中加入和除去原子的绝缘体上的应变半导体

    公开(公告)号：US08361889B2

    公开(公告)日：2013-01-29

    申请号：US12830626

    申请日：2010-07-06

    申请人： Thomas N. Adam ,  Stephen W. Bedell ,  Joel P. de Souza ,  Keith E. Fogel ,  Alexander Reznicek ,  Devendra K. Sadana ,  Ghavam G. Shahidi

    发明人： Thomas N. Adam ,  Stephen W. Bedell ,  Joel P. de Souza ,  Keith E. Fogel ,  Alexander Reznicek ,  Devendra K. Sadana ,  Ghavam G. Shahidi

    IPC分类号： H01L21/20

    CPC分类号： H01L29/1054 ,  H01L29/7833

    摘要： A method of forming a strained semiconductor-on-insulator (SSOI) substrate that does not include wafer bonding is provided. In this disclosure a relaxed and doped silicon layer is formed on an upper surface of a silicon-on-insulator (SOI) substrate. In one embodiment, the dopant within the relaxed and doped silicon layer has an atomic size that is smaller than the atomic size of silicon and, as such, the in-plane lattice parameter of the relaxed and doped silicon layer is smaller than the in-plane lattice parameter of the underlying SOI layer. In another embodiment, the dopant within the relaxed and doped silicon layer has an atomic size that is larger than the atomic size of silicon and, as such, the in-plane lattice parameter of the relaxed and doped silicon layer is larger than the in-plane lattice parameter of the underlying SOI layer. After forming the relaxed and doped silicon layer on the SOI substrate, the dopant within the relaxed and doped silicon layer is removed from that layer converting the relaxed and doped silicon layer into a strained (compressively or tensilely) silicon layer that is formed on an upper surface of an SOI substrate.

    摘要翻译： 提供了一种形成不包括晶片接合的应变绝缘体上半导体（SSOI）衬底的方法。 在本公开中，在绝缘体上硅（SOI）衬底的上表面上形成松弛和掺杂的硅层。 在一个实施例中，松弛和掺杂硅层内的掺杂剂具有小于硅的原子尺寸的原子尺寸，因此松弛和掺杂硅层的面内晶格参数小于硅的原子尺寸， 下层SOI层的平面晶格参数。 在另一实施例中，松弛和掺杂硅层内的掺杂剂具有大于硅的原子尺寸的原子尺寸，因此松弛和掺杂硅层的面内晶格参数大于硅原子尺寸， 下层SOI层的平面晶格参数。 在SOI衬底上形成松弛和掺杂的硅层之后，从该层去除松弛和掺杂硅层内的掺杂剂，将松散和掺杂的硅层转化成形成在上层的应变（压缩或拉伸）硅层 SOI衬底的表面。