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1.发明授权Apparatus and method for early issue and recovery for a conditional load instruction having multiple outcomes 有权用于具有多个结果的条件加载指令的早期发行和恢复的装置和方法公开(公告)号：US08977837B2
公开(公告)日：2015-03-10
申请号：US12453938
申请日：2009-05-27
CPC分类号： G06F9/3861 , G06F9/3001 , G06F9/30043 , G06F9/30072 , G06F9/3863
摘要： At least one instruction of a sequence of program instructions has a plurality of alternative outcomes including at least a first outcome that is independent of at least one operand and a second outcome that is dependent on the at least one operand. The at least one operand is a value generated by a preceding instruction in the sequence. The at least one instruction is issued for execution independently of when the at least one operand is generated by the preceding instruction. Recovery circuitry is provided to perform a recovery operation in the event that the second outcome is to be executed for the at least one instruction and the at least one operand has not been generated by the preceding instruction when the at least one instruction is to be executed by said instruction execution circuitry.
摘要翻译： 程序指令序列的至少一个指令具有多个替代结果，其包括至少独立于至少一个操作数的第一结果和取决于至少一个操作数的第二结果。 该至少一个操作数是由序列中的前一条指令产生的值。 当至少一个操作数由前一个指令生成时，发出至少一个指令用于执行。 提供恢复电路以在要执行至少一个指令的第二结果的情况下执行恢复操作，并且当要执行至少一个指令时，所述至少一个操作数尚未被前一指令生成 由所述指令执行电路。
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2.发明申请公开(公告)号：US20100306504A1
公开(公告)日：2010-12-02
申请号：US12453938
申请日：2009-05-27
CPC分类号： G06F9/3861 , G06F9/3001 , G06F9/30043 , G06F9/30072 , G06F9/3863
摘要： At least one instruction of a sequence of program instructions has a plurality of alternative outcomes including at least a first outcome that is independent of at least one operand and a second outcome that is dependent on the at least one operand. The at least one operand is a value generated by a preceding instruction in the sequence. The instruction is issued for execution independently of when the at least one operand is generated by the preceding instruction. Recovery circuitry is provided to perform a recovery operation in the event that the second outcome is executed for the at least one instruction and the at least one operand has not been generated by the preceding instruction when the at least one instruction is to be executed by said instruction execution circuitry.
摘要翻译： 程序指令序列的至少一个指令具有多个替代结果，其包括至少独立于至少一个操作数的第一结果和取决于至少一个操作数的第二结果。 该至少一个操作数是由序列中的前一条指令产生的值。 无论何时由前一条指令产生至少一个操作数，该指令被执行以执行。 提供恢复电路以在对所述至少一个指令执行第二结果的情况下执行恢复操作，并且当所述至少一个指令将由所述至少一个指令执行时，所述至少一个操作数尚未由所述先前指令生成 指令执行电路。
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3.发明申请Data storage protocols to determine items stored and items overwritten in linked data stores 有权用于确定存储的项目的数据存储协议和链接数据存储中覆盖的项目公开(公告)号：US20100325358A1
公开(公告)日：2010-12-23
申请号：US12457812
申请日：2009-06-22
CPC分类号： G06F12/1027 , G06F12/1054 , G06F2212/682
摘要： A storage apparatus and method for storing a plurality of items is disclosed. The storage apparatus is configured to receive a first access request and a second access request for accessing respective items in a same clock cycle. The storage apparatus comprises: two stores each for storing a subset of the plurality of items, the first access request being routed to a first store and said second access request to a second store; miss detecting circuitry for detecting a miss where a requested item is not stored in the accessed store; item retrieving circuitry for retrieving an item whose access generated a miss from a further store; updating circuitry for selecting an item to overwrite in a respective one of the two stores in dependence upon an access history of the respective store, the updating circuitry being responsive to the miss detecting circuitry detecting the miss in an access to the first store and to at least one further condition to update both of the two stores with the item retrieved from the further store by overwriting the selected items.
摘要翻译： 公开了一种用于存储多个物品的存储装置和方法。 存储装置被配置为接收在相同时钟周期中访问各个项目的第一访问请求和第二访问请求。 存储装置包括：两个存储器，每个存储器用于存储多个项目的子集，第一访问请求被路由到第一存储器，并且所述第二访问请求传送到第二存储器; 用于检测未请求的未检测电路，其中所请求的项目不存储在所访问的存储器中; 项目检索电路，用于检索其访问从另一商店中产生未命中的项目; 更新电路，用于根据相应存储器的访问历史来选择要在两个存储器中的相应一个存储器中重写的项目，所述更新电路响应于所述未检测电路检测到对所述第一存储器的访问中的遗漏并且处于 至少一个进一步的条件是通过覆盖所选择的项目来更新从另外的商店检索的商品的两个商店。
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4.发明授权Method and apparatus with data storage protocols for maintaining consistencies in parallel translation lookaside buffers 有权具有用于在并行翻译后备缓冲器中维持一致性的数据存储协议的方法和装置公开(公告)号：US08255629B2
公开(公告)日：2012-08-28
申请号：US12457812
申请日：2009-06-22
CPC分类号： G06F12/1027 , G06F12/1054 , G06F2212/682
摘要： A storage apparatus receives a first and second access requests for accessing items in a same clock cycle. The apparatus includes two stores, each storing a subset of the plurality of items, the first access request being routed to a first store and the second access request to a second store; miss detecting circuitry for detecting a miss in the accessed store; item retrieving circuitry for retrieving an item whose access generated a miss from a further store; updating circuitry for selecting an item to overwrite in one of the two stores, the updating circuitry being responsive to the miss detecting circuitry detecting the miss in an access to the first or second store and to at least one further condition to update both of the two stores with the item retrieved from the further store by overwriting the selected items.
摘要翻译： 存储装置在相同的时钟周期中接收访问项目的第一和第二访问请求。 该设备包括两个存储器，每个存储器存储多个项目的子集，第一访问请求被路由到第一存储器，第二访问请求存储到第二存储器; 用于检测所访问存储器中的未命中的未检测电路; 项目检索电路，用于检索其访问从另一商店中产生未命中的项目; 更新电路，用于选择在所述两个存储中的一个存储中重写的项目，所述更新电路响应于所述未检测电路检测到访问所述第一或第二存储器的未命中，以及至少一个另外的条件来更新两者 通过覆盖所选项目，从另外的商店检索的商品。
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公开(公告)号：US20100217937A1
公开(公告)日：2010-08-26
申请号：US12379440
申请日：2009-02-20
CPC分类号： G06F12/0862 , G06F9/30043 , G06F9/383 , G06F12/127 , G06F2212/6028
摘要： A data processing apparatus is described which comprises a processor operable to execute a sequence of instructions and a cache memory having a plurality of cache lines operable to store data values for access by the processor when executing the sequence of instructions. A cache controller is also provided which comprises preload circuitry operable in response to a streaming preload instruction received at the processor to store data values from a main memory into one or more cache lines of the cache memory. The cache controller also comprises identification circuitry operable in response to the streaming preload instruction to identify one or more cache lines of the cache memory for preferential reuse. The cache controller also comprises cache maintenance circuitry operable to implement a cache maintenance operation during which selection of one or more cache lines for reuse is performed having regard to any preferred for reuse identification generated by the identification circuitry for cache lines of the cache memory. In this way, a single streaming preload instruction can be used to trigger both a preload of one or more cache lines of data values into the cache memory, and also to mark for preferential reuse another one or more cache lines of the cache memory.
摘要翻译： 描述了一种数据处理装置，其包括可操作以执行指令序列的处理器和具有多个高速缓存行的高速缓存存储器，该多个高速缓存行可操作以在执行指令序列时存储用于由处理器访问的数据值。 还提供了一种缓存控制器，其包括预加载电路，该预加载电路响应于在处理器处接收到的流预加载指令而可操作以将来自主存储器的数据值存储到高速缓存存储器的一个或多个高速缓存行。 高速缓存控制器还包括可响应于流预加载指令操作的识别电路，以识别用于优先重用的高速缓冲存储器的一个或多个高速缓存行。 高速缓存控制器还包括可操作以实现高速缓存维护操作的高速缓存维护电路，在该高速缓存维护操作期间，考虑到用于高速缓冲存储器的高速缓存行的识别电路的识别电路产生的重用标识的任何优选，执行用于重新使用的一个或多个高速缓 以这种方式，可以使用单个流预加载指令来将数据值的一个或多个高速缓存行的预加载触发到高速缓冲存储器中，并且还用于标记用于优先重用高速缓冲存储器的另一个或多个高速缓存行。
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