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    Substrate solution for back gate controlled SRAM with coexisting logic devices
    1.
    发明授权
    Substrate solution for back gate controlled SRAM with coexisting logic devices 有权
    用于具有共存逻辑器件的背栅控制SRAM的衬底解决方案

    公开(公告)号：US07838942B2

    公开(公告)日：2010-11-23

    申请号：US12144272

    申请日：2008-06-23

    申请人： Robert H. Dennard ,  Wilfried E. Haensch ,  Arvind Kumar ,  Robert J. Miller

    发明人： Robert H. Dennard ,  Wilfried E. Haensch ,  Arvind Kumar ,  Robert J. Miller

    IPC分类号： H01L29/76

    CPC分类号： H01L27/1108

    摘要： A semiconductor structure that includes at least one logic device region and at least one static random access memory (SRAM) device region wherein each device region includes a double gated field effect transistor (FET) wherein the back gate of each of the FET devices is doped to a specific level so as to improve the performance of the FET devices within the different device regions is provided. In particular, the back gate within the SRAM device region is more heavily doped than the back gate within the logic device region. In order to control short channel effects, the FET device within the logic device region includes a doped channel, while the FET device within the SRAM device region does not. A none uniform lateral doping profile with a low net doping beneath the source/drain regions and a high net doping underneath the channel would provide additional SCE control for the logic device.

    摘要翻译： 一种半导体结构，其包括至少一个逻辑器件区域和至少一个静态随机存取存储器（SRAM）器件区域，其中每个器件区域包括双门控场效应晶体管（FET），其中每个FET器件的背栅极掺杂 提供了特定的水平，以提高不同器件区域内的FET器件的性能。 特别地，SRAM器件区域内的背栅极比逻辑器件区域内的后栅极重掺杂。 为了控制短沟道效应，逻辑器件区域内的FET器件包括掺杂沟道，而SRAM器件区域内的FET器件不是。 在源极/漏极区域之下具有低净掺杂的非均匀横向掺杂分布和在沟道下方的高净掺杂将为逻辑器件提供附加的SCE控制。

    SUBSTRATE SOLUTION FOR BACK GATE CONTROLLED SRAM WITH COEXISTING LOGIC DEVICES
    2.
    发明申请
    SUBSTRATE SOLUTION FOR BACK GATE CONTROLLED SRAM WITH COEXISTING LOGIC DEVICES 有权
    用于具有共同逻辑设备的后盖控制SRAM的基板解决方案

    公开(公告)号：US20080258221A1

    公开(公告)日：2008-10-23

    申请号：US12144272

    申请日：2008-06-23

    申请人： Robert H. Dennard ,  Wilfried E. Haensch ,  Arvind Kumar ,  Robert J. Miller

    发明人： Robert H. Dennard ,  Wilfried E. Haensch ,  Arvind Kumar ,  Robert J. Miller

    IPC分类号： H01L27/11

    CPC分类号： H01L27/1108

    摘要： A semiconductor structure that includes at least one logic device region and at least one static random access memory (SRAM) device region wherein each device region includes a double gated field effect transistor (FET) wherein the back gate of each of the FET devices is doped to a specific level so as to improve the performance of the FET devices within the different device regions is provided. In particular, the back gate within the SRAM device region is more heavily doped than the back gate within the logic device region. In order to control short channel effects, the FET device within the logic device region includes a doped channel, while the FET device within the SRAM device region does not. A none uniform lateral doping profile with a low net doping beneath the source/drain regions and a high net doping underneath the channel would provide additional SCE control for the logic device.

    摘要翻译： 一种半导体结构，其包括至少一个逻辑器件区域和至少一个静态随机存取存储器（SRAM）器件区域，其中每个器件区域包括双门控场效应晶体管（FET），其中每个FET器件的背栅极掺杂 提供了特定的水平，以提高不同器件区域内的FET器件的性能。 特别地，SRAM器件区域内的背栅极比逻辑器件区域内的后栅极重掺杂。 为了控制短沟道效应，逻辑器件区域内的FET器件包括掺杂沟道，而SRAM器件区域内的FET器件不是。 在源极/漏极区域之下具有低净掺杂的非均匀横向掺杂分布和在沟道下方的高净掺杂将为逻辑器件提供附加的SCE控制。

    Substrate solution for back gate controlled SRAM with coexisting logic devices
    3.
    发明授权
    Substrate solution for back gate controlled SRAM with coexisting logic devices 有权
    用于具有共存逻辑器件的背栅控制SRAM的衬底解决方案

    公开(公告)号：US07417288B2

    公开(公告)日：2008-08-26

    申请号：US11311462

    申请日：2005-12-19

    申请人： Robert H. Dennard ,  Wilfried E. Haensch ,  Arvind Kumar ,  Robert J. Miller

    发明人： Robert H. Dennard ,  Wilfried E. Haensch ,  Arvind Kumar ,  Robert J. Miller

    IPC分类号： H01L29/76

    CPC分类号： H01L27/1108

    摘要： A semiconductor structure that includes at least one logic device region and at least one static random access memory (SRAM) device region wherein each device region includes a double gated field effect transistor (FET) wherein the back gate of each of the FET devices is doped to a specific level so as to improve the performance of the FET devices within the different device regions is provided. In particular, the back gate within the SRAM device region is more heavily doped than the back gate within the logic device region. In order to control short channel effects, the FET device within the logic device region includes a doped channel, while the FET device within the SRAM device region does not. A none uniform lateral doping profile with a low net doping beneath the source/drain regions and a high net doping underneath the channel would provide additional SCE control for the logic device.

    摘要翻译： 一种半导体结构，其包括至少一个逻辑器件区域和至少一个静态随机存取存储器（SRAM）器件区域，其中每个器件区域包括双门控场效应晶体管（FET），其中每个FET器件的背栅极掺杂 提供了特定的水平，以提高不同器件区域内的FET器件的性能。 特别地，SRAM器件区域内的背栅极比逻辑器件区域内的后栅极重掺杂。 为了控制短沟道效应，逻辑器件区域内的FET器件包括掺杂沟道，而SRAM器件区域内的FET器件不是。 在源极/漏极区域之下具有低净掺杂的非均匀横向掺杂分布和在沟道下方的高净掺杂将为逻辑器件提供附加的SCE控制。

    Low voltage single-input DRAM current-sensing amplifier
    4.
    发明授权
    Low voltage single-input DRAM current-sensing amplifier 有权
    低电压单输入DRAM电流检测放大器

    公开(公告)号：US06370072B1

    公开(公告)日：2002-04-09

    申请号：US09726377

    申请日：2000-11-30

    申请人： Robert H. Dennard ,  Arvind Kumar

    发明人： Robert H. Dennard ,  Arvind Kumar

    IPC分类号： G11C702

    CPC分类号： G11C7/067 ,  G11C7/18 ,  G11C11/4091 ,  G11C11/4097 ,  G11C2207/063 ,  G11C2207/2227

    摘要： In a DRAM memory circuit, a current sensing amplifier is provided that exploits the low impedance of a reference transistor biased in the sub-threshold regime to enable transfer of a small voltage swing on the bitline to result in a large voltage signal on a low capacitance sense node. Compared to conventional voltage sensing, reduced bitline-bitline coupling noise results because of the small bitline swing, potentially allowing more cells to be served by a sense amplifier because of weak dependence of sense amplifier on bit-line capacitance. Compared to previous current-sensing schemes, this invention allows no idling current. The current-sensing amplifier additionally may be used in conjunction with a hierarchical bitline scheme to further increase the number of cells served by each sense amplifier.

    摘要翻译： 在DRAM存储器电路中，提供电流感测放大器，其利用偏置在子阈值状态中的参考晶体管的低阻抗，以使得能够在位线上传送小的电压摆幅，从而在低电容上产生较大的电压信号 感知节点。 与常规电压感测相比，​​由于位线摆幅小而导致位线位线耦合噪声减小，由于读出放大器对位线电容的弱依赖性，潜在地允许更多的单元由读出放大器提供服务。 与以前的电流检测方案相比，本发明不允许空载电流。 电流检测放大器另外可以与分层位线方案结合使用，以进一步增加由每个读出放大器服务的单元的数量。

    SUBSTITUTION OF HANDWRITTEN TEXT WITH A CUSTOM HANDWRITTEN FONT
    6.
    发明申请
    SUBSTITUTION OF HANDWRITTEN TEXT WITH A CUSTOM HANDWRITTEN FONT 有权
    用自定义手柄取代手写文字

    公开(公告)号：US20160379048A1

    公开(公告)日：2016-12-29

    申请号：US14752529

    申请日：2015-06-26

    申请人： Arvind Kumar

    发明人： Arvind Kumar

    IPC分类号： G06K9/00 ,  G06K9/62 ,  G06T11/60

    CPC分类号： G06K9/00409 ,  G06K9/00355 ,  G06K9/00402 ,  G06K9/6256 ,  G06T11/203 ,  G06T11/60

    摘要： Systems, apparatuses and methods may provide font substitution based on a custom font. In one example, a custom handwritten font may be generated based on a comparison between handwritten sample text and training text. In another example, handwritten original text may be converted to unique machine text based on a substitution of the handwritten original text with the custom handwritten font. Thus, a user's handwriting may be converted to the user's own best or preferred handwriting.

    摘要翻译： 系统，设备和方法可以提供基于定制字体的字体替换。 在一个示例中，可以基于手写样本文本和训练文本之间的比较来生成自定义手写字体。 在另一个例子中，手写的原始文本可以基于用手写字体代替手写的原始文本而被转换为唯一的机器文本。 因此，用户的笔迹可以被转换成用户自己的最佳或优选的笔迹。