公开(公告)号：US5533036A

公开(公告)日：1996-07-02

申请号：US486628

申请日：1995-06-07

申请人： Robert M. Blake ,  Douglas C. Bossen ,  Chin-Long Chen ,  John A. Fifield ,  Howard L. Kalter

发明人： Robert M. Blake ,  Douglas C. Bossen ,  Chin-Long Chen ,  John A. Fifield ,  Howard L. Kalter

IPC分类号： G06F11/00 ,  G06F11/10

CPC分类号： G06F11/1052 ,  G06F11/1008

摘要： In a memory system comprising a plurality of memory units each of which possesses unit-level error correction capabilities and each of which are tied to a system level error correction function, memory reliability is enhanced by providing means for disabling the unit-level error correction capability, for example, in response to the occurrence of an uncorrectable error in one of the memory units. This counter-intuitive approach which disables an error correction function nonetheless enhances overall memory system reliability since it enables the employment of the complement/recomplement algorithm which depends upon the presence of reproducible errors for proper operation. Thus, chip level error correction systems, which are increasingly desirable at high packaging densities, are employed in a way which does not interfere with system level error correction methods.

摘要翻译： 在包括多个存储器单元的存储器系统中，每个存储器单元具有单位级错误校正能力，并且每个存储器单元都与系统级错误校正功能相关联，通过提供用于禁用单元级错误校正能力的装置来增强存储器可靠性 例如，响应于在一个存储器单元中出现不可校正的错误。 这种禁用纠错功能的反直觉方法仍然提高了整体存储系统的可靠性，因为它可以使用补充/重新补充算法，这取决于是否存在可重复的错误以进行正确的操作。 因此，在高封装密度下越来越需要的芯片级误差校正系统采用不干扰系统级误差校正方法的方式。

公开(公告)号：US5228046A

公开(公告)日：1993-07-13

申请号：US790797

申请日：1991-11-12

申请人： Robert M. Blake ,  Douglas C. Bossen ,  Chin-Long Chen ,  John A. Fifield ,  Howard L. Kalter

发明人： Robert M. Blake ,  Douglas C. Bossen ,  Chin-Long Chen ,  John A. Fifield ,  Howard L. Kalter

IPC分类号： G06F11/00 ,  G06F11/10

CPC分类号： G06F11/1052 ,  G06F11/1008

摘要： In a memory system comprising a plurality of memory units each of which possesses unit-level error correction capabilities and each of which are tied to a system level error correction function, memory reliability is enhanced by providing a mechanism for disabling the unit-level error correction capability, for example, in response to the occurrence of an uncorrectable error in one of the memory units. This counter-intuitive approach which disables an error correction function nonetheless enhances overall memory system reliability since it enables the employment of the complement/recomplement algorithm which depends upon the presence of reproducible errors for proper operation. Thus, chip level error correction systems, which are increasingly desirable at high packaging densities, are employed in a way which does not interfere with system level error correction methods.

摘要翻译： 在包括多个存储器单元的存储器系统中，每个存储器单元具有单位级纠错能力，并且每个存储单元都与系统级错误校正功能相关联，通过提供用于禁用单位级错误校正的机制来增强存储器可靠性 能力，例如，响应于在一个存储器单元中发生不可校正的错误。 这种禁用纠错功能的反直觉方法仍然提高了整体存储系统的可靠性，因为它可以使用补充/重新补充算法，这取决于是否存在可重复的错误以进行正确的操作。 因此，在高封装密度下越来越需要的芯片级误差校正系统采用不干扰系统级误差校正方法的方式。

公开(公告)号：US5058115A

公开(公告)日：1991-10-15

申请号：US322255

申请日：1989-03-10

申请人： Robert M. Blake ,  Douglas C. Bossen ,  Chin-Long Chen ,  John A. Fifield ,  Howard L. Kalter ,  Tin-Chee Lo

发明人： Robert M. Blake ,  Douglas C. Bossen ,  Chin-Long Chen ,  John A. Fifield ,  Howard L. Kalter ,  Tin-Chee Lo

IPC分类号： G06F12/16 ,  G06F11/10

CPC分类号： G06F11/1052 ,  G06F11/1008

摘要： In a memory system comprising a plurality of memory units each of which possesses unit-level error correction capabilities and each of which are tied to a system level error correction function, memory reliability is enhanced by providing means for fixing the output of one of the memory units at a fixed value in response to the occurrence of an uncorrectable error in one of the memory units. This counter-intuitive approach to the generation of forced hard errors nonetheless enhances overall memory system reliability since it enables the employment of the complement/recomplement algorithm which depends upon the presence of reproducible errors for proper operation. Thus, clip level error correction systems, which are increasingly desirable at high packaging densities, are employed in a way which does not interfere with system level error correction methods.

公开(公告)号：US5581567A

公开(公告)日：1996-12-03

申请号：US401297

申请日：1995-03-09

申请人： Chin-Long Chen ,  John A. Fifield ,  Howard L. Kalter ,  Willem B. van der Hoeven

发明人： Chin-Long Chen ,  John A. Fifield ,  Howard L. Kalter ,  Willem B. van der Hoeven

IPC分类号： G06F11/10 ,  G06F12/16 ,  G11C29/00 ,  G11C29/42

CPC分类号： G06F11/1008

摘要： A memory system that provides extra data bits without utilizing storage capacity. A first data word is fetched from memory and corrected to remove any single-bit errors. A second data word (which is a subset of the first data word as corrected) is then fetched, and new data correction bits (parity or ECC check bits) is generated for the second data word. Both the second data word and the newly-generated data correction bits are output. This structure amortizes the expense of in-system data correction over a greater data output, and over a smaller storage capacity relative to the data output.

摘要翻译： 一种提供额外数据位而不占用存储容量的存储器系统。 从存储器中取出第一个数据字，并进行纠正以消除任何单位错误。 然后取出第二数据字（其是被校正的第一数据字的子集），并且为第二数据字生成新的数据校正位（奇偶校验位或ECC校验位）。 输出第二数据字和新产生的数据校正位。 该结构通过更大的数据输出和相对于数据输出的较小的存储容量来摊销系统内数据校正的费用。

公开(公告)号：US5031151A

公开(公告)日：1991-07-09

申请号：US600944

申请日：1990-10-22

申请人： John A. Fifield ,  Howard L. Kalter ,  Christopher P. Miller ,  Steven W. Thomashot

发明人： John A. Fifield ,  Howard L. Kalter ,  Christopher P. Miller ,  Steven W. Thomashot

IPC分类号： G11C29/00

CPC分类号： G11C29/84

摘要： A semiconductor memory device is described in which wordline redundancy is implemented without impacting the access time. A redundant decoder circuit generates a wordline drive inhibit signal which inhibits the generation of a normal wordline signal. Deselection also deselects the normally accessed reference cells, requiring that the redundant cells provide their own reference signal. This last requirement is accomplished by utilization of twin cells for the redundant memory. Placing the redundant memory cells on the sense node side of the bit line isolators enables the effective doubling of the number of redundant cells available to each of a plurality of sub-arrays of normal memory.

摘要翻译： 描述了在不影响访问时间的情况下实现字线冗余的半导体存储器件。 冗余解码器电路产生禁止产生正常字线信号的字线驱动禁止信号。 取消选择也取消选择通常访问的参考单元，要求冗余单元提供自己的参考信号。 最后一个要求是通过利用双电池来实现冗余存储器。 将冗余存储器单元放置在位线隔离器的感测节点侧使得能够有效地加倍可用于正常存储器的多个子阵列中的每一个的冗余单元。

公开(公告)号：US5134616A

公开(公告)日：1992-07-28

申请号：US479145

申请日：1990-02-13

申请人： John E. Barth, Jr. ,  Charles E. Drake ,  John A. Fifield ,  William P. Hovis ,  Howard L. Kalter ,  Scott C. Lewis ,  Daniel J. Nickel ,  Charles H. Stapper ,  James A. Yankosky

发明人： John E. Barth, Jr. ,  Charles E. Drake ,  John A. Fifield ,  William P. Hovis ,  Howard L. Kalter ,  Scott C. Lewis ,  Daniel J. Nickel ,  Charles H. Stapper ,  James A. Yankosky

IPC分类号： G11C11/401 ,  G06F11/10 ,  G11C29/00 ,  G11C29/42

CPC分类号： G11C29/84 ,  G06F11/1008

摘要： A DRAM having on-chip ECC and both bit and word redundancy that have been optimized to support the on-chip ECC. The bit line redundancy features a switching network that provides an any-for-any substitution for the bit lines in the associated memory array. The word line redundancy is provided in a separate array section, and has been optimized to maximize signal while reducing soft errors. The array stores data in the form of error correction words (ECWs) on each word line. A first set of data lines (formed in a zig-zag pattern to minimize unequal capacitive loading on the underlying bit lines) are coupled to read out an ECW as well as the redundant bit lines. A second set of data lines receive the ECW as corrected by bit line redundancy, and a third set of data lines receive the ECW as corrected by the word line redundancy. The third set of data lines are coupled to the ECC block, which corrects errors encountered in the ECW. The ECC circuitry is optimized to reduce the access delays introduced by carrying out on-chip error correction. The ECC block provides both the corrected data bits and the check bits to an SRAM. Thus, the check bits can be externally accessed. At the same time, having a set of interrelated bits in the SRAM compensates for whatever access delays are introduced by the ECC. To maximize the efficiency of switching from mode to mode, the modes are set as a function of received address signals.

公开(公告)号：US5010524A

公开(公告)日：1991-04-23

申请号：US340962

申请日：1989-04-20

申请人： John A. Fifield ,  Howard L. Kalter

发明人： John A. Fifield ,  Howard L. Kalter

IPC分类号： G11C11/401 ,  G11C7/18 ,  G11C11/4097

CPC分类号： G11C11/4097 ,  G11C7/18

摘要： This invention relates to semiconductor memories and includes a sense amplifier architecture in which sensed data bit or column lines are electrically isolated and shielded from their immediately adjacent active neighbors by utilization of non-selected bit lines as an AC ground bus. In its simplest embodiment, shielded bit line (SBL) architecture includes two pairs of opposed bit lines associated with a common sense amplifier. One of each of the bit line pairs is multiplexed into the sense amplifier and the other unselected bit line pair is clamped to AC ground to shield the selected bit line pair from all dynamic line-to-line coupling.

公开(公告)号：US06177809B1

公开(公告)日：2001-01-23

申请号：US09322470

申请日：1999-05-28

申请人： William R. Tonti ,  Jack A. Mandelman ,  Anthony R. Bonaccio ,  Claude L. Bertin ,  Howard L. Kalter ,  John A. Fifield

发明人： William R. Tonti ,  Jack A. Mandelman ,  Anthony R. Bonaccio ,  Claude L. Bertin ,  Howard L. Kalter ,  John A. Fifield

IPC分类号： H03K19094

CPC分类号： H03K19/00384 ,  H03K19/0005

摘要： A first, “known good” reference off-chip driver circuit actuated by an initial logic program (IPL) input signal has an output lead connected as one of the inputs to a comparator circuit for providing a reference off-chip driver output signal. A second off-chip driver circuit including a plurality of “n” separate driver circuit paths connected to input signal and produces output signals connected to a common node to provide output driver signals to the common node. The common node is connected to the second input of the comparator circuit for comparison with the reference off-chip driver output signal from the first off-chip driver circuit to determine the operating state of the second off-chip driver circuit with respect to the operating state of the first off-chip driver circuit.

摘要翻译： 由初始逻辑程序（IPL）输入信号驱动的第一个“已知的良好”参考芯片外驱动电路具有作为输入端之一的输出引线连接到比较器电路，用于提供参考片外驱动器输出信号。 包括连接到输入信号的多个“n”个分离的驱动器电路路径并产生连接到公共节点的输出信号以向公共节点提供输出驱动器信号的第二片外驱动器电路。 公共节点连接到比较器电路的第二输入，用于与来自第一片外驱动器电路的参考芯片外驱动器输出信号进行比较，以确定第二片外驱动器电路相对于操作的运行状态 状态的第一个片外驱动电路。

公开(公告)号：US5563086A

公开(公告)日：1996-10-08

申请号：US406284

申请日：1995-03-17

申请人： Claude L. Bertin ,  Wayne J. Howell ,  Erik L. Hedberg ,  Howard L. Kalter ,  Gordon A. Kelley, Jr.

发明人： Claude L. Bertin ,  Wayne J. Howell ,  Erik L. Hedberg ,  Howard L. Kalter ,  Gordon A. Kelley, Jr.

IPC分类号： G11C5/00 ,  H01L25/065 ,  H01L21/70

CPC分类号： H01L25/0657 ,  G11C5/06 ,  H01L2224/48091 ,  H01L2225/0651 ,  H01L2225/06551 ,  H01L2225/06555 ,  H01L2225/06572 ,  H01L2225/06596 ,  H01L2924/10253

摘要： An integrated memory cube structure and method of fabrication wherein stacked semiconductor memory chips are integrated by a controlling logic chip such that a more powerful memory architecture is defined with the functional appearance of a single, higher level memory chip. A memory/logic cube is formed having N memory chips and at least one logic chip, with each memory chip of the cube having M memory devices. The controlling logic chip coordinates external communication with the N memory chips such that a single memory chip architecture with N.times.M memory devices appears at the cube's I/O pins. A corresponding fabrication technique includes an approach for facilitating metallization patterning on the side surface of the memory subunit.

摘要翻译： 一种集成的存储立方体结构和制造方法，其中堆叠的半导体存储器芯片由控制逻辑芯片集成，使得更强大的存储器架构被定义为单个更高级存储器芯片的功能外观。 形成具有N个存储器芯片和至少一个逻辑芯片的存储器/逻辑立方体，其中立方体的每个存储器芯片具有M个存储器件。 控制逻辑芯片协调与N个存储器芯片的外部通信，使得具有NxM存储器件的单个存储器芯片架构出现在立方体的I / O引脚处。 相应的制造技术包括用于在存储器子单元的侧表面上促进金属化图案化的方法。

公开(公告)号：US4603341A

公开(公告)日：1986-07-29

申请号：US530452

申请日：1983-09-08

申请人： Claude L. Bertin ,  Howard L. Kalter

发明人： Claude L. Bertin ,  Howard L. Kalter

IPC分类号： G11C17/08 ,  H01L21/822 ,  H01L21/8246 ,  H01L27/00 ,  H01L27/06 ,  H01L27/10 ,  H01L27/112 ,  H01L29/78 ,  G11C17/00

CPC分类号： H01L27/11519 ,  H01L21/8221 ,  H01L27/0688 ,  H01L27/112

摘要： A read only memory array of stacked IGFET devices composed of first and second sub-arrays of field effect transistors. The first sub-array of first field effect transistors is formed in a substrate. Each of the first field effect transistor devices is responsive to a polysilicon gate electrode. The second sub-array of second field effect transistors is formed in a layer of laser annealed polysilicon material which overlies the first sub-array. The gate electrodes of the first field effect transistors act as the gate electrodes of the second field effect transistors.

摘要翻译： 由场效应晶体管的第一和第二子阵列组成的堆叠IGFET器件的只读存储器阵列。 第一场效应晶体管的第一子阵列形成在衬底中。 第一场效应晶体管器件中的每一个都响应于多晶硅栅电极。 第二场效应晶体管的第二子阵列形成在覆盖在第一子阵列上的激光退火多晶硅材料层中。 第一场效应晶体管的栅电极用作第二场效应晶体管的栅电极。