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    Integrated circuit and design structure having reduced through silicon via-induced stress
    4.
    发明授权
    Integrated circuit and design structure having reduced through silicon via-induced stress 有权
    集成电路和设计结构通过硅通孔引起的应力降低

    公开(公告)号：US09406562B2

    公开(公告)日：2016-08-02

    申请号：US13005883

    申请日：2011-01-13

    申请人： Jeffrey P. Bonn ,  Brent A. Goplen ,  Brian L. Kinsman ,  Robert M. Rassel ,  Edmund J. Sprogis ,  Daniel S. Vanslette

    发明人： Jeffrey P. Bonn ,  Brent A. Goplen ,  Brian L. Kinsman ,  Robert M. Rassel ,  Edmund J. Sprogis ,  Daniel S. Vanslette

    IPC分类号： H01L23/48 ,  H01L21/768 ,  G06F17/50

    CPC分类号： H01L21/76898 ,  G06F17/5068 ,  G06F2217/80 ,  H01L23/481 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Embodiments of the invention provide an integrated circuit (IC) having reduced through silicon via (TSV)-induced stresses and related IC design structures and methods. In one embodiment, the invention includes a method of designing an integrated circuit (IC) having reduced substrate stress, the method including: placing in an IC design file a plurality of through silicon via (TSV) placeholder cells, each placeholder cell having an undefined TSV orientation; replacing a first portion of the plurality of TSV placeholder cells with a first group of TSV cells having a first orientation; and replacing a second portion of the plurality of TSV placeholder cells with a second group of TSV cells having a second orientation substantially perpendicular to the first orientation, wherein TSV cells having the first orientation and TSV cells having the second orientation are interspersed to reduce a TSV-induced stress in an IC substrate.

    摘要翻译： 本发明的实施例提供了具有减少的通过硅通孔（TSV）的应力和相关IC设计结构和方法的集成电路（IC）。 在一个实施例中，本发明包括设计具有降低的衬底应力的集成电路（IC）的方法，所述方法包括：在IC设计文件中放置多个通过硅通孔（TSV）占位符单元，每个占位符单元具有未定义的 TSV方向 用具有第一取向的第一组TSV单元替换所述多个TSV占位符单元的第一部分; 以及用具有基本上垂直于第一取向的第二取向的第二组TSV单元替换多个TSV占位符单元的第二部分，其中具有第一取向的TSV单元和具有第二取向的TSV单元分散以减少TSV 在IC衬底中引起的应力。

    INTEGRATED CIRCUIT AND DESIGN STRUCTURE HAVING REDUCED THROUGH SILICON VIA-INDUCED STRESS
    7.
    发明申请
    INTEGRATED CIRCUIT AND DESIGN STRUCTURE HAVING REDUCED THROUGH SILICON VIA-INDUCED STRESS 有权
    集成电路和通过硅通过感应应力减少的设计结构

    公开(公告)号：US20120181700A1

    公开(公告)日：2012-07-19

    申请号：US13005883

    申请日：2011-01-13

    申请人： Jeffrey P. Bonn ,  Brent A. Goplen ,  Brian L. Kinsman ,  Robert M. Rassel ,  Edmund J. Sprogis ,  Daniel S. Vanslette

    发明人： Jeffrey P. Bonn ,  Brent A. Goplen ,  Brian L. Kinsman ,  Robert M. Rassel ,  Edmund J. Sprogis ,  Daniel S. Vanslette

    IPC分类号： H01L23/48 ,  G06F17/50

    CPC分类号： H01L21/76898 ,  G06F17/5068 ,  G06F2217/80 ,  H01L23/481 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Embodiments of the invention provide an integrated circuit (IC) having reduced through silicon via (TSV)-induced stresses and related IC design structures and methods. In one embodiment, the invention includes a method of designing an integrated circuit (IC) having reduced substrate stress, the method including: placing in an IC design file a plurality of through silicon via (TSV) placeholder cells, each placeholder cell having an undefined TSV orientation; replacing a first portion of the plurality of TSV placeholder cells with a first group of TSV cells having a first orientation; and replacing a second portion of the plurality of TSV placeholder cells with a second group of TSV cells having a second orientation substantially perpendicular to the first orientation, wherein TSV cells having the first orientation and TSV cells having the second orientation are interspersed to reduce a TSV-induced stress in an IC substrate.

    摘要翻译： 本发明的实施例提供了具有减少的通过硅通孔（TSV）的应力和相关IC设计结构和方法的集成电路（IC）。 在一个实施例中，本发明包括设计具有降低的衬底应力的集成电路（IC）的方法，所述方法包括：在IC设计文件中放置多个通过硅通孔（TSV）占位符单元，每个占位符单元具有未定义的 TSV方向 用具有第一取向的第一组TSV单元替换所述多个TSV占位符单元的第一部分; 以及用具有基本上垂直于第一取向的第二取向的第二组TSV单元替换多个TSV占位符单元的第二部分，其中具有第一取向的TSV单元和具有第二取向的TSV单元分散以减少TSV 在IC衬底中引起的应力。

    Method of forming refractory metal contact in an opening, and resulting structure
    9.
    发明授权
    Method of forming refractory metal contact in an opening, and resulting structure 失效
    在开口中形成难熔金属接触的方法，以及结果

    公开(公告)号：US06900505B2

    公开(公告)日：2005-05-31

    申请号：US10709174

    申请日：2004-04-19

    申请人： Jonanthan D. Chapple-Sokol ,  Randy W. Mann ,  William J. Murphy ,  Jed H. Rankin ,  Daniel S. Vanslette

    发明人： Jonanthan D. Chapple-Sokol ,  Randy W. Mann ,  William J. Murphy ,  Jed H. Rankin ,  Daniel S. Vanslette

    IPC分类号： C23C28/00 ,  H01L31/119

    CPC分类号： C23C28/00 ,  Y10T428/12

    摘要： A structure which ensures against deterioration of an underlying silicide layer over which a refractory material layer is deposited by physical vapor deposition (PVD) or chemical vapor deposition (CVD) is realized by first providing a continuous polysilicon layer prior to the refractory material deposition. The continuous polysilicon layer, preferably no thicker than 50 Å, serves a sacrificial purpose and prevents damage to an underlying silicide layer by blocking interaction between any fluorine and the underlying silicide that is released when the refractory material is formed.

    摘要翻译： 通过首先在耐火材料沉积之前提供连续的多晶硅层，来实现通过物理气相沉积（PVD）或化学气相沉积（CVD）来确保防止耐火材料层沉积下层硅化物层的劣化的结构。 连续多晶硅层优选不大于50，用于牺牲目的，并且通过阻止在形成耐火材料时释放的任何氟和下面的硅化物之间的相互作用来防止对下面的硅化物层的损伤。

    Structure with a metal silicide transparent conductive electrode and a method of forming the structure
    10.
    发明授权
    Structure with a metal silicide transparent conductive electrode and a method of forming the structure 有权
    具有金属硅化物透明导电电极的结构和形成该结构的方法

    公开(公告)号：US09312426B2

    公开(公告)日：2016-04-12

    申请号：US13313101

    申请日：2011-12-07

    申请人： Jeffrey P. Gambino ,  Derrick Liu ,  Daniel S. Vanslette

    发明人： Jeffrey P. Gambino ,  Derrick Liu ,  Daniel S. Vanslette

    IPC分类号： H05K1/09 ,  B05D5/12 ,  B82Y99/00 ,  H01L31/18 ,  H01L31/0224 ,  H01L33/00 ,  H01L33/42 ,  H01L51/00 ,  B82Y10/00 ,  B82Y30/00 ,  H01B1/24 ,  H05K3/10

    CPC分类号： H01L31/1884 ,  B82Y10/00 ,  B82Y30/00 ,  H01B1/24 ,  H01L31/022408 ,  H01L31/022425 ,  H01L31/022466 ,  H01L33/005 ,  H01L33/42 ,  H01L51/0021 ,  H05K3/105 ,  H05K2201/0108 ,  H05K2201/026 ,  H05K2203/1194 ,  Y02E10/50

    摘要： Disclosed are embodiments of a structure with a metal silicide transparent conductive electrode, which is commercially viable, robust and safe to use and, thus, optimal for incorporation into devices, such as flat panel displays, touch panels, solar cells, light emitting diodes (LEDs), organic optoelectronic devices, etc. Specifically, the structure can comprise a substrate (e.g., a glass or plastic substrate) and a transparent conducting film on that substrate. The transparent conducting film can comprise a metal silicide nanowire network. For example, in one embodiment, the metal silicide nanowire network can comprise multiple metal silicide nanowires fused together in a disorderly arrangement so that they form a mesh. In another embodiment, the metal silicide nanowire network can comprise multiple metal silicide nanowires patterned so that they form a grid. Also disclosed herein are various different method embodiments for forming such a structure.

    摘要翻译： 公开了具有金属硅化物透明导电电极的结构的实施例，其具有商业上可行性，稳健且安全使用，并且因此最佳地结合到诸如平板显示器，触摸面板，太阳能电池，发光二极管 LED），有机光电子器件等。具体地，该结构可以包括衬底（例如，玻璃或塑料衬底）和该衬底上的透明导电膜。 透明导电膜可以包括金属硅化物纳米线网络。 例如，在一个实施例中，金属硅化物纳米线网络可以包括以无序布置融合在一起的多个金属硅化物纳米线，使得它们形成网状物。 在另一个实施例中，金属硅化物纳米线网络可以包括图案化的多个金属硅化物纳米线，使得它们形成网格。 这里还公开了用于形成这种结构的各种不同的方法实施例。