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    REDUCING CONTAMINATION OF SEMICONDUCTOR SUBSTRATES DURING BEOL PROCESSING BY PROVIDING A PROTECTION LAYER AT THE SUBSTRATE EDGE
    5.
    发明申请
    REDUCING CONTAMINATION OF SEMICONDUCTOR SUBSTRATES DURING BEOL PROCESSING BY PROVIDING A PROTECTION LAYER AT THE SUBSTRATE EDGE 有权
    通过在基板边缘处提供保护层来减少烧结过程中半导体基板的污染

    公开(公告)号：US20080003830A1

    公开(公告)日：2008-01-03

    申请号：US11625579

    申请日：2007-01-22

    申请人： Su Ruo Qing ,  Frank Feustel ,  Carsten Peters

    发明人： Su Ruo Qing ,  Frank Feustel ,  Carsten Peters

    IPC分类号： H01L21/311

    CPC分类号： H01L21/76801 ,  H01L21/02087 ,  H01L21/3043 ,  H01L21/31144 ,  H01L21/76802

    摘要： By providing a protection layer at the bevel region, the deposition of polymer materials during the patterning process of complex metallization structures may be reduced. Additionally or alternatively, a surface topography may be provided, for instance in the form of respective recesses, in order to enhance the degree of adhesion of any materials deposited in the bevel region during the manufacturing of complex metallization structures. Advantageously, the provision of the protection layer providing the reduced polymer deposition may be combined with the modified surface topography.

    摘要翻译： 通过在斜面区域设置保护层，可以减少复杂金属化结构的图形化过程期间聚合物材料的沉积。 附加地或替代地，可以提供例如各自凹部的形式的表面形貌，以便在复杂金属化结构的制造期间增强沉积在斜面区域中的任何材料的粘附程度。 有利的是，提供提供降低的聚合物沉积的保护层可以与改性表面形貌组合。

    DUAL INTEGRATION SCHEME FOR LOW RESISTANCE METAL LAYERS
    6.
    发明申请
    DUAL INTEGRATION SCHEME FOR LOW RESISTANCE METAL LAYERS 审中-公开
    低电阻金属层的双重整合方案

    公开(公告)号：US20090108462A1

    公开(公告)日：2009-04-30

    申请号：US12104692

    申请日：2008-04-17

    申请人： Carsten Peters ,  Frank Feustel ,  Kai Frohberg

    发明人： Carsten Peters ,  Frank Feustel ,  Kai Frohberg

    IPC分类号： H01L23/48 ,  H01L21/4763

    CPC分类号： H01L23/53295 ,  H01L21/76808 ,  H01L21/76816 ,  H01L21/76832 ,  H01L21/76834 ,  H01L23/5226 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

    摘要： By forming a metal line extending through the entire interlayer dielectric material in resistance sensitive metallization layers, enhanced uniformity of these metallization layers may be obtained. The patterning of respective via openings may be accomplished on the basis of a recess formed in a cap layer, which additionally acts as an efficient etch stop layer during the patterning of the trenches, which extend through the entire interlayer dielectric material. Consequently, for a given design width of metal lines in resistance sensitive metallization layers, a maximum cross-sectional area may be obtained for the metal line with a high degree of process uniformity irrespective of a variation of the via density.

    摘要翻译： 通过在电阻敏感的金属化层中形成延伸穿过整个层间电介质材料的金属线，可获得这些金属化层的均匀性。 相应过孔开口的图案化可以基于形成在盖层中的凹槽来实现，该凹槽在沟槽图案化期间另外充当有效的蚀刻停止层，其延伸穿过整个层间电介质材料。 因此，对于电阻敏感金属化层中金属线的给定设计宽度，可以获得具有高程度均匀性的金属线的最大横截面积，而与通孔密度的变化无关。

    Method of selectively forming a conductive barrier layer by ALD
    7.
    发明授权
    Method of selectively forming a conductive barrier layer by ALD 有权
    通过ALD选择性地形成导电阻挡层的方法

    公开(公告)号：US08173538B2

    公开(公告)日：2012-05-08

    申请号：US11757022

    申请日：2007-06-01

    申请人： Frank Feustel ,  Carsten Peters ,  Thomas Foltyn

    发明人： Frank Feustel ,  Carsten Peters ,  Thomas Foltyn

    IPC分类号： H01L21/4763

    CPC分类号： H01L21/76844

    摘要： By providing a surface modification process prior to or during a self-limiting deposition process, the per se highly conformal deposition behavior may be selectively changed so as to obtain reliable coverage at specific surface areas, while significantly reducing or suppressing a deposition above unwanted surface areas, such as the bottom of a via in advanced metallization structures of highly scaled semiconductor devices.

    摘要翻译： 通过在自限制沉积工艺之前或期间提供表面改性方法，可以选择性地改变本身高共形沉积行为，以便在比表面积获得可靠的覆盖，同时显着地减少或抑制不想要的表面积 ，例如高分辨率半导体器件的先进金属化结构中的通孔的底部。

    Test structure for monitoring leakage currents in a metallization layer
    8.
    发明授权
    Test structure for monitoring leakage currents in a metallization layer 有权
    用于监测金属化层中的漏电流的测试结构

    公开(公告)号：US07764078B2

    公开(公告)日：2010-07-27

    申请号：US11623372

    申请日：2007-01-16

    申请人： Frank Feustel ,  Thomas Werner ,  Carsten Peters

    发明人： Frank Feustel ,  Thomas Werner ,  Carsten Peters

    IPC分类号： G01R31/26 ,  G01R31/36 ,  H01L23/58

    CPC分类号： H01L22/34 ,  H01L2924/0002 ,  H01L2924/00

    摘要： By providing a plurality of resistors and a plurality of test patterns within a leakage current test structure, the number of probe pads required for estimating the plurality of test patterns may be significantly reduced, wherein, in some illustrative embodiments, several test patterns may be simultaneously assessed on the basis of two probe pads. Consequently, process parameters and/or design parameters for manufacturing metallization structures of semiconductor devices may be efficiently monitored and controlled.

    摘要翻译： 通过在泄漏电流测试结构内提供多个电阻器和多个测试图案，可以显着地减少用于估计多个测试图案所需的探针焊盘的数量，其中在一些说明性实施例中，可以同时进行几个测试图案 基于两个探针垫进行评估。 因此，可以有效地监测和控制用于制造半导体器件的金属化结构的工艺参数和/或设计参数。

    TEST STRUCTURE FOR MONITORING LEAKAGE CURRENTS IN A METALLIZATION LAYER
    10.
    发明申请
    TEST STRUCTURE FOR MONITORING LEAKAGE CURRENTS IN A METALLIZATION LAYER 有权
    用于监测金属化层中漏电流的测试结构

    公开(公告)号：US20070296439A1

    公开(公告)日：2007-12-27

    申请号：US11623372

    申请日：2007-01-16

    申请人： Frank Feustel ,  Thomas Werner ,  Carsten Peters

    发明人： Frank Feustel ,  Thomas Werner ,  Carsten Peters

    IPC分类号： G01R31/02

    CPC分类号： H01L22/34 ,  H01L2924/0002 ,  H01L2924/00

    摘要： By providing a plurality of resistors and a plurality of test patterns within a leakage current test structure, the number of probe pads required for estimating the plurality of test patterns may be significantly reduced, wherein, in some illustrative embodiments, several test patterns may be simultaneously assessed on the basis of two probe pads. Consequently, process parameters and/or design parameters for manufacturing metallization structures of semiconductor devices may be efficiently monitored and controlled.

    摘要翻译： 通过在泄漏电流测试结构内提供多个电阻器和多个测试图案，可以显着地减少用于估计多个测试图案所需的探针焊盘的数量，其中在一些说明性实施例中，可以同时进行几个测试图案 基于两个探针垫进行评估。 因此，可以有效地监测和控制用于制造半导体器件的金属化结构的工艺参数和/或设计参数。