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21 条记录 (耗时 0.019 秒)

    Data processing device with loop pipeline
    1.
    发明授权
    Data processing device with loop pipeline 失效
    带循环管线的数据处理装置

    公开(公告)号：US6085315A

    公开(公告)日：2000-07-04

    申请号：US928444

    申请日：1997-09-12

    申请人： Rod G. Fleck ,  Venkat Mattela ,  Eric Chesters ,  Muhammad Afsar

    发明人： Rod G. Fleck ,  Venkat Mattela ,  Eric Chesters ,  Muhammad Afsar

    IPC分类号： G06F9/32 ,  G06F9/38 ,  G06F9/45

    CPC分类号： G06F9/3885 ,  G06F9/325 ,  G06F9/3804

    摘要： The data processing device according to the invention comprises an instruction providing unit having an input and an output, a pipeline unit for processing data having input and output stages, a loop pipeline unit for processing a loop instruction having input and output stages, said input stages of said pipeline units being coupled to said output of said instruction providing unit, said instruction providing unit providing data for said pipelines, and said pipeline units processing said data independently.

    摘要翻译： 根据本发明的数据处理装置包括具有输入和输出的指令提供单元，用于处理具有输入和输出级的数据的流水线单元，用于处理具有输入和输出级的循环指令的循环流水线单元，所述输入级 所述管线单元耦合到所述指令提供单元的所述输出，所述指令提供单元为所述管线提供数据，所述流水线单元独立地处理所述数据。

    System and method for arranging, accessing and distributing data to achieve zero cycle penalty for access crossing a cache line
    2.
    发明授权
    System and method for arranging, accessing and distributing data to achieve zero cycle penalty for access crossing a cache line 失效
    用于安排，访问和分发数据以实现跨越高速缓存行的访问的零周期损失的系统和方法

    公开(公告)号：US06226707B1

    公开(公告)日：2001-05-01

    申请号：US08972054

    申请日：1997-11-17

    申请人： Venkat Mattela ,  Muhammad Afsar

    发明人： Venkat Mattela ,  Muhammad Afsar

    IPC分类号： G06F1206

    CPC分类号： G06F9/3816 ,  G06F12/0851 ,  G06F12/0886

    摘要： A data processing system and method for arranging and accessing information that crosses cache lines utilize dual cache columns. The dual cache columns are formed of two access-related cache lines. The two cache columns contain sequential information that is stored in cache lines in a sequential and alternating format. A processor makes a request for a particular instruction. An instruction fetch unit takes the instruction request and creates a second instruction request in addition to the first instruction request. The two instruction requests are sent simultaneously to first and second content addressable memories (CAMs) respectively associated with the first and second cache columns. The CAMs are simultaneously searched and any cache hits are forwarded to a switch. The switch combines the relevant portions of the two cache lines and delivers the desired instruction to a processor. A method of accessing and distributing stored data in a computer system is also described. The method includes generating the data to be distributed by combining relevant segments from simultaneously accessed first and second cache lines.

    摘要翻译： 用于布置和访问跨越高速缓存行的信息的数据处理系统和方法利用双缓存列。 双缓存列由两个访问相关的缓存行组成。 两个缓存列包含以顺序和交替格式存储在高速缓存行中的顺序信息。 一个处理器请求一个特定的指令。 指令提取单元接收指令请求，并且除了第一指令请求之外还创建第二指令请求。 两个指令请求被同时发送到分别与第一和第二高速缓存列相关联的第一和第二内容可寻址存储器（CAM）。 同时搜索CAM，并将任何缓存命中转发到交换机。 交换机组合了两条高速缓存行的相关部分，并将所需的指令传递给处理器。 还描述了在计算机系统中访问和分发存储的数据的方法。 该方法包括通过组合来自同时访问的第一和第二高速缓存行的相关段来生成要分发的数据。

    Memory activation devices and methods
    3.
    发明授权
    Memory activation devices and methods 有权
    内存激活设备和方法

    公开(公告)号：US6040998A

    公开(公告)日：2000-03-21

    申请号：US132559

    申请日：1998-08-11

    申请人： Chih-Ta Star Sung ,  Venkat Mattela ,  Muhammad Afsar ,  Balraj Singh ,  Chih-Teng Hung

    发明人： Chih-Ta Star Sung ,  Venkat Mattela ,  Muhammad Afsar ,  Balraj Singh ,  Chih-Teng Hung

    IPC分类号： G11C8/18 ,  G11C7/00 ,  G11C8/00

    CPC分类号： G11C8/18

    摘要： An apparatus and method are disclosed for activating a memory location within a memory device. In an apparatus aspect of the invention, a memory device is disclosed. The memory device includes an enable unit arranged to receive a plurality of address signals and a clock signal and to output an activation signal. The address signals has an associated worst case delay, and the enable unit is further arranged to generate an enable signal that is delayed from the clock signal by at least about the worst case delay. The memory device further includes a memory array arranged to receive the activation signal in response to which a corresponding memory location is activated.

    摘要翻译： 公开了用于激活存储器件内的存储器位置的装置和方法。 在本发明的装置方面，公开了一种存储器件。 存储器件包括一个使能单元，其被布置为接收多个地址信号和时钟信号并输出​​激活信号。 所述地址信号具有相关联的最坏情况延迟，并且所述使能单元进一步被布置为产生从所述时钟信号延迟至少约最坏情况延迟的使能信号。 存储器件还包括存储器阵列，其布置成接收激活信号，响应于该激活信号激活对应的存储器位置。

    Mobile Femto-cell in a Wireless Safety Network
    4.
    发明申请
    Mobile Femto-cell in a Wireless Safety Network 有权
    无线安全网络中的移动毫微微小区

    公开(公告)号：US20110217947A1

    公开(公告)日：2011-09-08

    申请号：US13039477

    申请日：2011-03-03

    申请人： Stanislaw Czaja ,  Muhammad Afsar

    发明人： Stanislaw Czaja ,  Muhammad Afsar

    IPC分类号： H04M11/04

    CPC分类号： H04M11/045 ,  H04M1/72577 ,  H04M11/04 ,  H04W72/04 ,  H04W84/005 ,  H04W84/10

    摘要： This invention provides wireless safety network through the integration of mobile femto-cells (mFAP), into macro-cellular system. Such network provides safety management for students during their travel to and from school through the supervision of handovers between home and mobile femto-cell and the macro-cellular environment as well as supervision of class attendance, emergency function, and other services.

    摘要翻译： 本发明通过将移动毫微微小区（mFAP）集成到宏蜂窝系统中来提供无线安全网络。 这样的网络通过监督家庭和移动毫微微小区和宏蜂窝环境之间的切换，以及对班级出勤，应急功能和其他业务的监督，为学生上学期间提供安全管理。

    Method and system for detecting bypass error conditions in a load/store unit of a superscalar processor
    6.
    发明授权
    Method and system for detecting bypass error conditions in a load/store unit of a superscalar processor 失效
    用于检测超标量处理器的加载/存储单元中的旁路错误状况的方法和系统

    公开(公告)号：US5751946A

    公开(公告)日：1998-05-12

    申请号：US588183

    申请日：1996-01-18

    申请人： Muhammad Afsar ,  Christopher Anthony Freymuth

    发明人： Muhammad Afsar ,  Christopher Anthony Freymuth

    IPC分类号： G06F9/38 ,  G06F11/28

    CPC分类号： G06F9/3834

    摘要： A method for detecting bypass error conditions in a load/store unit of a superscalar processor includes determining whether a load instruction has executed out-of-order with respect to an executing store instruction when a real address to a word boundary of the load instruction and a real address to a word boundary of the executing store instruction match, and identifying a bypass error condition for the load instruction when the load instruction has executed out-of-order with respect to the executing store instruction. In a system aspect, the system includes a load queue, detection logic, and completion logic. The load queue includes a real page number buffer for storing a real address to a word boundary for each executed load instruction. The detection logic compares real addresses to a word boundary for a load instruction against an executing store instruction and compares a program order of the load instruction and the executing store instruction when the real addresses to a word boundary match. The completion logic receives the executing store instruction and a bypass error signal when the load instruction has executed out-of-order with respect to the executing store instruction. The completion logic also receives the identifier of the load instruction which bypassed the executing store instruction.

    摘要翻译： 一种用于检测超标量处理器的加载/存储单元中的旁路错误状况的方法，包括：当实际地址到加载指令的字边界时，确定加载指令是否相对于执行存储指令执行无序， 执行存储指令的字边界的真实地址匹配，以及当所述加载指令相对于执行存储指令执行无序时，识别所述加载指令的旁路错误条件。 在系统方面，系统包括负载队列，检测逻辑和完成逻辑。 负载队列包括用于将实际地址存储到每个执行的加载指令的字边界的实际页号缓冲器。 检测逻辑将实际地址与针对执行存储指令的加载指令的字边界进行比较，并且当实际地址到字边界匹配时，将加载指令的程序顺序和执行存储指令进行比较。 当加载指令相对于执行存储指令执行无序时，完成逻辑接收执行存储指令和旁路错误信号。 完成逻辑还接收绕过执行存储指令的加载指令的标识符。

    Method and/or apparatus for generating a write gated clock signal
    7.
    发明授权
    Method and/or apparatus for generating a write gated clock signal 有权
    用于产生写门控时钟信号的方法和/或装置

    公开(公告)号：US07046066B2

    公开(公告)日：2006-05-16

    申请号：US10867899

    申请日：2004-06-15

    申请人： Alon Saado ,  Linley M. Young ,  Muhammad Afsar

    发明人： Alon Saado ,  Linley M. Young ,  Muhammad Afsar

    IPC分类号： G06F1/04

    CPC分类号： G06F1/32 ,  G06F1/10 ,  G11C2029/3202

    摘要： An apparatus comprising a first circuit and a second circuit. The first circuit may be configured to generate a gated clock signal in response to (i) a write enable signal and (ii) a system clock signal. The gated clock signal is pulsed active while the write enable signal is active. The second circuit may be configured to generate the write enable signal.

    摘要翻译： 一种包括第一电路和第二电路的装置。 第一电路可以被配置为响应于（i）写使能信号和（ii）系统时钟信号而产生门控时钟信号。 当写使能信号有效时，门控时钟信号是脉冲激活的。 第二电路可以被配置为产生写使能信号。

    Method and/or apparatus implemented in hardware to discard bad logical transmission units (LTUs)
    9.
    发明申请
    Method and/or apparatus implemented in hardware to discard bad logical transmission units (LTUs) 有权
    在硬件中实现的丢弃不良逻辑传输单元（LTU）的方法和/或装置

    公开(公告)号：US20050251717A1

    公开(公告)日：2005-11-10

    申请号：US10842376

    申请日：2004-05-10

    申请人： Alon Saado ,  Muhammad Afsar

    发明人： Alon Saado ,  Muhammad Afsar

    IPC分类号： G01R31/28 ,  G06F11/00 ,  H03M13/00 ,  H04L1/00 ,  H04L1/20

    CPC分类号： H04L1/0052 ,  H04L1/0061

    摘要： The present invention concerns an apparatus comprising a logic circuit, a compare circuit, a control circuit and a memory interface. The logic circuit may be configured to generate a check signal in response to (i) a data signal having a series of logical transmission units (LTUs) and (ii) a first control signal. The compare circuit may be configured to generate a compare signal in response to the check signal and the data signal. The control circuit configured to generate (i) the first control signal and (ii) a second control signal indicating a valid or invalid status of each of the LTUs, in response to a data valid signal and the compare signal. The memory interface may be configured to generate an output data signal in response to the second control signal. The memory interface is generally configured to store only the LTUs having a valid status.

    摘要翻译： 本发明涉及包括逻辑电路，比较电路，控制电路和存储器接口的装置。 逻辑电路可以被配置为响应于（i）具有一系列逻辑传输单元（LTU）的数据信号和（ii）第一控制信号而产生检查信号。 比较电路可以被配置为响应于检查信号和数据信号而产生比较信号。 所述控制电路经配置以响应于数据有效信号和所述比较信号产生（i）所述第一控制信号和（ii）指示每个所述LTU的有效或无效状态的第二控制信号。 存储器接口可以被配置为响应于第二控制信号而产生输出数据信号。 存储器接口通常被配置为仅存储具有有效状态的LTU。

    Dynamic data prefetching based on program counter and addressing mode
    10.
    发明授权
    Dynamic data prefetching based on program counter and addressing mode 有权
    基于程序计数器和寻址模式的动态数据预取

    公开(公告)号：US06401193B1

    公开(公告)日：2002-06-04

    申请号：US09178052

    申请日：1998-10-26

    申请人： Muhammad Afsar ,  Klaus Oberlaender

    发明人： Muhammad Afsar ,  Klaus Oberlaender

    IPC分类号： G06F930

    CPC分类号： G06F12/0862 ,  G06F9/383 ,  G06F9/3832 ,  G06F2212/6028

    摘要： Prefetching data to a low level memory of a computer system is accomplished utilizing an instruction location indicator related to an upcoming instruction to identify a next data prefetch indicator and then utilizing the next data prefetch indicator to locate the corresponding prefetch data within the memory of the computer system. The prefetch data is located so that the prefetch data can be transferred to a primary cache where the data can be quickly fetched by a processor when the upcoming instruction is executed. The next data prefetch indicator is generated by carrying out the addressing mode function that is embedded in an instruction only when the addressing mode of the instruction is a deterministic addressing mode such as a sequential. The next data prefetch indicator, preferably in the form of an effective address, is identified by the instruction location indicator, preferably in the form of a program counter, by relating calculated next effective addresses to corresponding program counter tags in a searchable table.

    摘要翻译： 使用与即将到来的指令相关的指令位置指示符来预取数据到计算机系统的低级存储器，以识别下一个数据预取指示符，然后利用下一个数据预取指示符来定位计算机的存储器内的相应的预取数据 系统。 预取数据被定位成使得预取数据可以被传送到主缓存，其中当执行即将到来的指令时，可以由处理器快速地获取数据。 只有当指令的寻址模式是诸如顺序的确定性寻址模式时，才通过执行嵌入在指令中的寻址模式功能来生成下一个数据预取指示符。 优选地以有效地址的形式的下一个数据预取指示符通过指令位置指示符，优选地以程序计数器的形式通过将计算的下一个有效地址与可搜索表中的相应程序计数器标签相关联来识别。