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4 条记录 (耗时 0.028 秒)

    Dotting circuit with inhibit function
    2.
    发明授权
    Dotting circuit with inhibit function 失效
    带抑制功能的点阵电路

    公开(公告)号：US4743781A

    公开(公告)日：1988-05-10

    申请号：US882058

    申请日：1986-07-03

    申请人： Harsaran S. Bhatia ,  Harry J. Jones ,  Shashi D. Malaviya

    发明人： Harsaran S. Bhatia ,  Harry J. Jones ,  Shashi D. Malaviya

    IPC分类号： H03K19/082 ,  H03K19/086 ,  H03K19/173 ,  H03K19/013 ,  H03K17/04 ,  H03K17/60

    CPC分类号： H03K19/1738 ,  H03K19/086

    摘要： A new dotting circuit for integrated circuit chips which provides line switching, as well as simultaneous true and complementary outputs, while eliminating the need for the standard collector circuit voltage clamp. This circuit is implemented by the collector dotting of two or more input transistors, the collector dotting of their respective reference transistors, the emitter dotting of one input transistor and a reference transistor to a constant current source, the emitter dotting of the other input transistor and the other reference transistor to a different constant current source, and an inhibit circuit for permitting current to flow to only one of the emitter-dotted circuits in accordance with a logic control signal.

    摘要翻译： 用于集成电路芯片的新型点阵电路，提供线路切换，以及同时的真实和互补输出，同时不需要标准集电极电压钳位。 该电路由两个或多个输入晶体管的集电极点，其各自的参考晶体管的集电极点，一个输入晶体管的发射极点和参考晶体管连接到恒定电流源，另一个输入晶体管的发射极点 另一个参考晶体管连接到不同的恒流源，以及禁止电路，用于根据逻辑控制信号允许电流仅流向发射极点电路中的一个。

    Electronic EC for minimizing EC pads
    3.
    发明授权
    Electronic EC for minimizing EC pads 失效
    电子EC用于最小化EC垫

    公开(公告)号：US4746815A

    公开(公告)日：1988-05-24

    申请号：US881755

    申请日：1986-07-03

    申请人： Harsaran S. Bhatia ,  Mario E. Ecker ,  Harry J. Jones ,  Shashi D. Malaviya

    发明人： Harsaran S. Bhatia ,  Mario E. Ecker ,  Harry J. Jones ,  Shashi D. Malaviya

    IPC分类号： H01L21/82 ,  G06F1/22 ,  H01L21/822 ,  H01L23/538 ,  H01L27/04 ,  H03K3/26 ,  H03K3/335

    CPC分类号： G06F1/22 ,  H01L23/5382 ,  H01L2924/0002 ,  Y10T307/492

    摘要： A specially designed module and integrated circuit chip therefor which permits the sharing of module EC pads between chip receiver and driver circuits. The chip has a direct normal input line to each receiver circuit therein and a direct normal output line from each driver circuit therein along with signal lines from each of those circuits to various EC pads. The chip further includes a switching and control circuit for switching the receiver circuits and driver circuits between their normal and EC lines to effect an electronic delete function. In a preferred embodiment, a majority of the EC pads are switchably connected via the switching and control circuit to different sets of three adjacent receiver circuits, driver circuits, or a combination thereof. The design permits the use of approximately half the EC pads normally required for a module, while permitting EC connections to be made in most cases to three adjacent receiver or driver circuits simultaneously.

    摘要翻译： 一种特别设计的模块和集成电路芯片，允许在芯片接收器和驱动器电路之间共享模块EC焊盘。 该芯片具有其中每个接收器电路的直接正常输入线和来自其中每个驱动器电路的直接正常输出线以及从这些电路中的每一个到各种EC焊盘的信号线。 该芯片还包括用于在其正常和EC线路之间切换接收器电路和驱动器电路以实现电子删除功能的开关和控制电路。 在优选实施例中，大部分EC焊盘通过开关和控制电路可切换地连接到不同组的三个相邻接收器电路，驱动电路或其组合。 该设计允许使用模块通常需要的大约一半的EC焊盘，同时允许在大多数情况下同时向三个相邻的接收器或驱动器电路进行EC连接。

    Process for making a dual implanted drain extension for bucket brigade device tetrode structure
    4.
    发明授权
    Process for making a dual implanted drain extension for bucket brigade device tetrode structure 失效
    用于铲斗装备四级结构的双注入漏极延伸的工艺

    公开(公告)号：US4358890A

    公开(公告)日：1982-11-16

    申请号：US293903

    申请日：1981-08-18

    申请人： Lawrence G. Heller ,  Harry J. Jones ,  Harish N. Kotecha ,  Donald A. Soderman

    发明人： Lawrence G. Heller ,  Harry J. Jones ,  Harish N. Kotecha ,  Donald A. Soderman

    IPC分类号： H01L21/8234 ,  H01L27/07 ,  H01L27/105 ,  H01L29/08 ,  H01L29/10 ,  H01L21/26

    CPC分类号： H01L27/1055 ,  H01L21/823406 ,  H01L27/0733 ,  H01L29/0847 ,  H01L29/1045

    摘要： The invention is the structure and process for making a bucket brigade device which comprises the merger of an MOS capacitor with an MOSFET device to form the charge transfer cell. A first thin N-type region is implanted at a first concentration in a portion of the P-type channel region of an FET device adjacent to the drain diffusion. A second region is implanted with N-type dopant at a second concentration less than the first concentration, adjacent to and continuous with the first implanted region. The N-type concentration in the second region is just sufficient to compensate for the P-type background doping in the channel region. This structure increases the charge transfer efficiency for the cell and reduces its sensitivity of the threshold voltage to the source-drain voltage. The gate for the device has a substantial overlap over the drain and a minimal overlap over the source and the gate to drain capacitance per unit area is maximized by maintaining a uniformly thin oxide layer across the gate region.

    摘要翻译： 本发明是用于制造桶式装置的结构和工艺，其包括MOS电容器与MOSFET器件的合并以形成电荷转移电池。 在与漏极扩散相邻的FET器件的P型沟道区域的一部分中以第一浓度注入第一薄N型区域。 第二区域以与第一注入区域相邻并与第一注入区域连续的第一浓度的第二浓度注入N型掺杂剂。 第二区域中的N型浓度刚好足以补偿沟道区域中的P型背景掺杂。 这种结构增加了电池的电荷转移效率，并降低了其阈值电压对源极 -​​ 漏极电压的灵敏度。 用于器件的栅极在漏极上具有实质重叠，并且源极上的最小重叠，并且通过在栅极区域上保持均匀薄的氧化物层来最大化每单位面积的栅极至漏极电容。