公开(公告)号：US5369358A

公开(公告)日：1994-11-29

申请号：US965472

申请日：1992-10-23

申请人： Roland Metzger ,  Manfred Schmidt ,  Otto Torreiter ,  Dieter Wendel

发明人： Roland Metzger ,  Manfred Schmidt ,  Otto Torreiter ,  Dieter Wendel

IPC分类号： G01R1/067 ,  G01R1/073 ,  G01R31/28 ,  G01R1/04

CPC分类号： G01R1/07314 ,  G01R1/06794 ,  G01R31/2886

摘要： A method of testing chips having each a plurality of contact pads, the chips are arranged on a semiconductor wafer or on a printed circuit and are tested with a test system having a test head provided with a plurality of probes, the method comprising the steps of: a) moving the test head and the chips towards each other by a distance which is smaller than a predefined maximum length; b) determining the presence of a contact between the probes and the contact pads by performing an electrical test via the probes to yield a predetermined electrical result; and c) repeating steps a) and b) until the electrical test no longer yields the predetermined electrical result or until the predefined maximum length is reached. The invention also provides for a test system for carrying out the inventive method.

摘要翻译： 一种测试具有多个接触焊盘的芯片的方法，所述芯片布置在半导体晶片上或印刷电路上，并且用具有设置有多个探针的测试头的测试系统测试，所述方法包括以下步骤： ：a）将测试头和芯片朝向彼此移动一个小于预定最大长度的距离; b）通过经由探针的电测试来确定探针和接触垫之间的接触的存在以产生预定的电结果; 以及c）重复步骤a）和b），直到电测试不再产生预定的电气结果或直到达到预定的最大长度。 本发明还提供了用于实施本发明方法的测试系统。

公开(公告)号：US5742616A

公开(公告)日：1998-04-21

申请号：US486468

申请日：1995-06-07

申请人： Otto Torreiter ,  Roland Metzger ,  Dieter Wendel

发明人： Otto Torreiter ,  Roland Metzger ,  Dieter Wendel

IPC分类号： G06F11/10 ,  G06F12/14 ,  G06F12/16 ,  G06F15/78 ,  G06F21/00 ,  G06F21/24 ,  G11C29/40 ,  G11C29/44 ,  G01R31/28

CPC分类号： G06F21/79 ,  G06F12/1466 ,  G06F21/64 ,  G11C29/40 ,  G11C29/44 ,  G06F11/1004

摘要： A self test circuit provides a general statement about the condition of a coupled memory which indicates whether a wanted or unwanted manipulation or alteration of the memory has occurred. The contents of the memory are not derivable from the general statement. The general statement is preferably a "fail" or "pass" statement stating whether a deviation in the contents of the memory with respect to a last executed test has been detected or not. The testing of a non-volatile memory is executed by generating a signature from the contents of the non-volatile memory and comparing the generated signature with a reference value of the signature. When the comparison of the generated signature with the reference value indicates a different, a signal is issued and access to the non-volatile memory is restricted and/or a failure procedure is started. Access to the non-volatile memory is allowed when the comparison signature with the reference value indicates no difference. In order to allow a test of whether an alteration of the contents of the non-volatile memory has happened between successive authorized applications, a new signature from the contents of the non-volatile memory is generated after each application and stored as a new reference value.

摘要翻译： 自检电路提供关于耦合存储器的状况的一般说明，其指示是否发生了想要的或不需要的操作或改变存储器。 内存的内容不能从一般语句中推导出来。 一般性声明优选地是“失败”或“通过”声明，说明是否已经检测到相对于最后执行的测试的存储器的内容的偏差。 通过从非易失性存储器的内容生成签名并将生成的签名与签名的参考值进行比较来执行非易失性存储器的测试。 当生成的签名与参考值的比较指示不同时，发出信号并且限制访问非易失性存储器和/或启动故障过程。 当与参考值的比较签名没有差异时，允许访问非易失性存储器。 为了允许在连续授权的应用程序之间发生非易失性存储器的内容的改变的测试，在每个应用程序之后生成来自非易失性存储器的内容的新签名，并将其存储为新的参考值 。

公开(公告)号：US08866504B2

公开(公告)日：2014-10-21

申请号：US13280626

申请日：2011-10-25

申请人： Martin Eckert ,  Roland Frech ,  Otto Torreiter ,  Dieter Wendel

发明人： Martin Eckert ,  Roland Frech ,  Otto Torreiter ,  Dieter Wendel

IPC分类号： G01R31/3187 ,  G01R31/317

CPC分类号： G01R31/3187 ,  G01R31/31703

摘要： A system for measuring a test voltage level (Vx) in a location within a chip is presented. The system includes an on-chip measurement device with an on-chip comparator and an on-chip storage. The on-chip comparator is configured for comparing the test voltage (Vx) to be measured to a reference voltage (Vref), while the on-chip storage is configured for storing the result of this comparison. The system also includes external (off-chip) equipment for generating the reference voltage (Vref), for generating probe signals for probing the state of the storage and for retrieving the state of said on-chip storage.

摘要翻译： 提出了一种用于测量芯片内部位置的测试电压电平（Vx）的系统。 该系统包括具有片上比较器和片上存储器的片上测量装置。 片上比较器被配置为将待测量的测试电压（Vx）与参考电压（Vref）进行比较，而片上存储被配置用于存储该比较的结果。 该系统还包括用于产生参考电压（Vref）的外部（片外）设备，用于产生用于探测存储器的状态并检索所述片上存储器的状态的探测信号。

公开(公告)号：US20120146674A1

公开(公告)日：2012-06-14

申请号：US13280626

申请日：2011-10-25

申请人： Martin Eckert ,  Roland Frech ,  Otto Torreiter ,  Dieter Wendel

发明人： Martin Eckert ,  Roland Frech ,  Otto Torreiter ,  Dieter Wendel

IPC分类号： G01R31/3187

CPC分类号： G01R31/3187 ,  G01R31/31703

摘要： A system for measuring a test voltage level (Vx) in a location within a chip is presented. The system includes an on-chip measurement device with an on-chip comparator and an on-chip storage. The on-chip comparator is configured for comparing the test voltage (Vx) to be measured to a reference voltage (Vref), while the on-chip storage is configured for storing the result of this comparison. The system also includes external (off-chip) equipment for generating the reference voltage (Vref), for generating probe signals for probing the state of the storage and for retrieving the state of said on-chip storage.

摘要翻译： 提出了一种用于测量芯片内部位置的测试电压电平（Vx）的系统。 该系统包括具有片上比较器和片上存储器的片上测量装置。 片上比较器被配置为将待测量的测试电压（Vx）与参考电压（Vref）进行比较，而片上存储被配置用于存储该比较的结果。 该系统还包括用于产生参考电压（Vref）的外部（片外）设备，用于产生用于探测存储器的状态并检索所述片上存储器的状态的探测信号。

公开(公告)号：US20070124637A1

公开(公告)日：2007-05-31

申请号：US11563702

申请日：2006-11-28

申请人： Gottfried Goldrian ,  Otto Torreiter ,  Dieter Wendel

发明人： Gottfried Goldrian ,  Otto Torreiter ,  Dieter Wendel

IPC分类号： G01R31/28

CPC分类号： G01R31/31725 ,  G01R31/31922

摘要： A method for performing a test of a high-speed integrated circuit with at least one functional unit and built-in self-test features by a low-speed test system. The method comprises the steps of transforming an external clock signal from the test system into a faster internal clock signal within the integrated circuit, generating a test pattern according to a predetermined scheme, and applying the test pattern to the functional unit, comparing a response from the functional unit with an expected test pattern. If the response differs from the expected test pattern, then an internal failure signal is generated and the internal failure signal is extended to a length, which may be recognized by the test system. Further the present invention relates to a high-speed integrated circuit with at least one functional unit and built-in self-test features.

摘要翻译： 一种用于通过低速测试系统执行具有至少一个功能单元的高速集成电路测试和内置自检特征的方法。 该方法包括以下步骤：将来自测试系统的外部时钟信号变换成集成电路内更快的内部时钟信号，根据预定方案生成测试模式，并将测试模式应用于功能单元，比较来自 具有预期测试模式的功能单元。 如果响应与预期测试模式不同，则产生内部故障信号，并将内部故障信号扩展到可被测试系统识别的长度。 此外，本发明涉及具有至少一个功能单元和内置自检特征的高速集成电路。

公开(公告)号：US07913132B2

公开(公告)日：2011-03-22

申请号：US12273985

申请日：2008-11-19

申请人： Tobias Gemmeke ,  Dieter Wendel ,  Holger Wetter ,  Jens Leenstra

发明人： Tobias Gemmeke ,  Dieter Wendel ,  Holger Wetter ,  Jens Leenstra

IPC分类号： G01R31/28

CPC分类号： G01R31/318536

摘要： A digital system and method for scanning sequential logic elements are disclosed. The digital system may comprise a plurality of sequential logic elements subdivided into power domains, wherein at least one of the power domains is power gated; a scan chain configured for processing a scan data sequence; a scan enable switch configured for controlling a scan mode; and at least one shadow engine, wherein the at least one shadow engine comprises a control circuit. At least some of the power domains may be interconnected to the scan chain with the scan enable switch, and the scan enable switch may control the scan mode by asserting a scan enable signal. The at least one power gated power domain with one or more sequential logic elements to be power gated may be bypassed via the at least one shadow engine.

摘要翻译： 公开了用于扫描顺序逻辑元件的数字系统和方法。 数字系统可以包括被分成多个功率域的多个顺序逻辑元件，其中至少一个功率域是功率选通; 配置用于处理扫描数据序列的扫描链; 配置成用于控制扫描模式的扫描使能开关; 和至少一个阴影引擎，其中所述至少一个阴影引擎包括控制电路。 至少一些功率域可以与扫描使能开关互连到扫描链，并且扫描使能开关可以通过断言扫描使能信号来控制扫描模式。 可以经由至少一个阴影引擎绕过具有一个或多个顺序逻辑元件以供电门控的至少一个电源门控功率域。

公开(公告)号：US07650554B2

公开(公告)日：2010-01-19

申请号：US11563702

申请日：2006-11-28

申请人： Gottfried Goldrian ,  Otto Andreas Torreiter ,  Dieter Wendel

发明人： Gottfried Goldrian ,  Otto Andreas Torreiter ,  Dieter Wendel

IPC分类号： G01R31/28 ,  G11C29/00

CPC分类号： G01R31/31725 ,  G01R31/31922

摘要： A method for performing a test of a high-speed integrated circuit with at least one functional unit and built-in self-test features by a low-speed test system. The method comprises the steps of transforming an external clock signal from the test system into a faster internal clock signal within the integrated circuit, generating a test pattern according to a predetermined scheme, and applying the test pattern to the functional unit, comparing a response from the functional unit with an expected test pattern. If the response differs from the expected test pattern, then an internal failure signal is generated and the internal failure signal is extended to a length, which may be recognized by the test system. Further the present invention relates to a high-speed integrated circuit with at least one functional unit and built-in self-test features.

摘要翻译： 一种用于通过低速测试系统执行具有至少一个功能单元的高速集成电路测试和内置自检特征的方法。 该方法包括以下步骤：将来自测试系统的外部时钟信号变换成集成电路内更快的内部时钟信号，根据预定方案生成测试模式，并将测试模式应用于功能单元，比较来自 具有预期测试模式的功能单元。 如果响应与预期测试模式不同，则产生内部故障信号，并将内部故障信号扩展到可被测试系统识别的长度。 此外，本发明涉及具有至少一个功能单元和内置自检特征的高速集成电路。

公开(公告)号：US07225419B2

公开(公告)日：2007-05-29

申请号：US10962121

申请日：2004-10-08

申请人： Erwin Behnen ,  Jeffrey P. Soreff ,  James D. Warnock ,  Dieter Wendel

发明人： Erwin Behnen ,  Jeffrey P. Soreff ,  James D. Warnock ,  Dieter Wendel

IPC分类号： G06F17/50

CPC分类号： G06F17/5022

摘要： In a first aspect, a method is provided that includes the steps of (1) receiving a circuit design having a plurality of latches; and (2) allowing one or more latches of the circuit design to be locally treated as exhibiting latch transparency during modeling of the timing behavior of the circuit design. Numerous other aspects are provided.

摘要翻译： 在第一方面中，提供了一种方法，包括以下步骤：（1）接收具有多个锁存器的电路设计; 以及（2）允许电路设计的一个或多个闩锁在电路设计的定时行为建模期间被局部处理为呈现闩锁透明度。 提供了许多其他方面。

公开(公告)号：US20050135179A1

公开(公告)日：2005-06-23

申请号：US11010902

申请日：2004-12-13

申请人： Martin Eckert ,  Juergen Pille ,  Dieter Wendel

发明人： Martin Eckert ,  Juergen Pille ,  Dieter Wendel

IPC分类号： G11C7/10 ,  G11C8/00 ,  G11C8/16

CPC分类号： G11C7/1075 ,  G11C8/16

摘要： A multiport array comprises a read section which is separated from an array of memory cells and which forms a plurality of data-out ports each consisting of a predetermined number of output lines. The read section comprises a multiplex network containing a plurality of multiplex arrays each associated with one of the data-out ports (0,1, . . . ,15). The multiplex arrays are connected to the data read lines of the memory cells and are selected by read addresses. The multiplex arrays comprise transmission elements which connect selected ones of the data read lines to the associated data-out port.

摘要翻译： 多端口阵列包括与存储器单元阵列分离并且形成多个数据输出端口的读取部件，每个数据输出端口由预定数量的输出线路组成。 读取部分包括多路复用网络，该多路复用网络包含多个多路复用阵列，每个多路复用阵列与数据输出端口（0,1，...，15）之一相关联。 多路复用阵列连接到存储单元的数据读取线，并通过读地址进行选择。 多路复用阵列包括将选定数据读取线连接到相关联的数据输出端口的传输元件。

公开(公告)号：US06219296B1

公开(公告)日：2001-04-17

申请号：US09597954

申请日：2000-06-20

申请人： George McNeil Lattimore ,  Dieter Wendel ,  Friedrich-Christian Wernicke

发明人： George McNeil Lattimore ,  Dieter Wendel ,  Friedrich-Christian Wernicke

IPC分类号： G11C800

CPC分类号： G11C8/16

摘要： A multiport memory cell having a reduced number of write wordlines is disclosed. The multiport memory cell capable of simultaneously reading data from and writing data to a storage cell comprises a storage cell for storing data, a decoder, write wordlines, write bitlines, read wordlines, and read bitlines. The write wordlines and the write bitlines are utilized to input write data into the storage cell. The read wordlines and the read bitlines are utilized to output data from the storage cell. The write bitlines are directly coupled to the storage cell, and some or all of the write wordlines are coupled to the storage cell via the decoder for the purpose of wire reduction. Similar to the write bitlines, all the read bitlines and read wordlines are directly coupled to the storage cell.

摘要翻译： 公开了具有减少数量的写字线的多端口存储单元。 能够同时从存储单元读取数据并将数据写入存储单元的多端口存储单元包括用于存储数据的存储单元，解码器，写字线，写位线，读字线和读位线。 写入字线和写位线用于将写入数据输入存储单元。 读取字线和读位线用于从存储单元输出数据。 写入位线直接耦合到存储单元，并且为了减少线的目的，部分或全部写入字线通过解码器耦合到存储单元。 与写入位线类似，所有读取的位线和读取字线都直接耦合到存储单元。