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    STRUCTURE OF POWER GRID FOR SEMICONDUCTOR DEVICES AND METHOD OF MAKING THE SAME
    1.
    发明申请
    STRUCTURE OF POWER GRID FOR SEMICONDUCTOR DEVICES AND METHOD OF MAKING THE SAME 失效
    半导体器件的电源结构及其制造方法

    公开(公告)号：US20120100712A1

    公开(公告)日：2012-04-26

    申请号：US13342221

    申请日：2012-01-03

    申请人： Ronald Filippi ,  Wai-kin Li ,  Ping-Chuan Wang

    发明人： Ronald Filippi ,  Wai-kin Li ,  Ping-Chuan Wang

    IPC分类号： H01L21/76

    CPC分类号： H01L23/5226 ,  H01L21/76802 ,  H01L21/76847 ,  H01L21/76852 ,  H01L23/5286 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53252 ,  H01L23/53266 ,  H01L2924/0002 ,  H01L2924/00

    摘要： An embodiment of the invention provides a semiconductor structure, which may include a stud of a first conductive material formed inside a dielectric layer; a via of a second conductive material having a bottom and sidewalls with the bottom and the sidewalls being covered by a conductive liner, and the bottom being formed directly on top of the stud and being in contact with the via through the conductive liner; and one or more conductive paths of a third conductive material connecting to the via through the conductive liner at the sidewalls of said the. A method of making the semiconductor structure is also provided.

    摘要翻译： 本发明的一个实施例提供一种半导体结构，其可以包括形成在电介质层内部的第一导电材料的支柱; 具有底部的第二导电材料的通孔和具有底部的侧壁，并且侧壁被导电衬垫覆盖，并且底部直接形成在螺柱的顶部上并且通过导电衬套与通孔接触; 以及一个或多个第三导电材料的导电路径，所述第三导电材料在所述导电衬套的侧壁处通过所述导电衬套连接到所述通孔。 还提供了制造半导体结构的方法。

    STRUCTURE OF POWER GRID FOR SEMICONDUCTOR DEVICES AND METHOD OF MAKING THE SAME
    2.
    发明申请
    STRUCTURE OF POWER GRID FOR SEMICONDUCTOR DEVICES AND METHOD OF MAKING THE SAME 有权
    半导体器件的电源结构及其制造方法

    公开(公告)号：US20100327445A1

    公开(公告)日：2010-12-30

    申请号：US12491372

    申请日：2009-06-25

    申请人： Ronald Filippi ,  Wai-kin Li ,  Ping-Chuan Wang

    发明人： Ronald Filippi ,  Wai-kin Li ,  Ping-Chuan Wang

    IPC分类号： H01L23/535 ,  H01L21/768

    CPC分类号： H01L23/5226 ,  H01L21/76802 ,  H01L21/76847 ,  H01L21/76852 ,  H01L23/5286 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53252 ,  H01L23/53266 ,  H01L2924/0002 ,  H01L2924/00

    摘要： An embodiment of the invention provides a semiconductor structure, which may include a stud of a first conductive material formed inside a dielectric layer; a via of a second conductive material having a bottom and sidewalls with the bottom and the sidewalls being covered by a conductive liner, and the bottom being formed directly on top of the stud and being in contact with the via through the conductive liner; and one or more conductive paths of a third conductive material connecting to the via through the conductive liner at the sidewalls of said the. A method of making the semiconductor structure is also provided.

    摘要翻译： 本发明的一个实施例提供一种半导体结构，其可以包括形成在电介质层内部的第一导电材料的支柱; 具有底部的第二导电材料的通孔和具有底部的侧壁，并且侧壁被导电衬垫覆盖，并且底部直接形成在螺柱的顶部上并且通过导电衬套与通孔接触; 以及一个或多个第三导电材料的导电路径，所述第三导电材料在所述导电衬套的侧壁处通过所述导电衬套连接到所述通孔。 还提供了制造半导体结构的方法。

    Structure of power grid for semiconductor devices and method of making the same
    3.
    发明授权
    Structure of power grid for semiconductor devices and method of making the same 失效
    半导体器件电网结构及其制作方法

    公开(公告)号：US08349723B2

    公开(公告)日：2013-01-08

    申请号：US13342221

    申请日：2012-01-03

    申请人： Ronald Filippi ,  Wai-kin Li ,  Ping-Chuan Wang

    发明人： Ronald Filippi ,  Wai-kin Li ,  Ping-Chuan Wang

    IPC分类号： H01L21/4763

    CPC分类号： H01L23/5226 ,  H01L21/76802 ,  H01L21/76847 ,  H01L21/76852 ,  H01L23/5286 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53252 ,  H01L23/53266 ,  H01L2924/0002 ,  H01L2924/00

    摘要： An embodiment of the invention provides a semiconductor structure, which may include a stud of a first conductive material formed inside a dielectric layer; a via of a second conductive material having a bottom and sidewalls with the bottom and the sidewalls being covered by a conductive liner, and the bottom being formed directly on top of the stud and being in contact with the via through the conductive liner; and one or more conductive paths of a third conductive material connecting to the via through the conductive liner at the sidewalls of said the. A method of making the semiconductor structure is also provided.

    摘要翻译： 本发明的一个实施例提供一种半导体结构，其可以包括形成在电介质层内部的第一导电材料的支柱; 具有底部的第二导电材料的通孔和具有底部的侧壁，并且侧壁被导电衬垫覆盖，并且底部直接形成在螺柱的顶部上并且通过导电衬套与通孔接触; 以及一个或多个第三导电材料的导电路径，所述第三导电材料在所述导电衬套的侧壁处通过所述导电衬套连接到所述通孔。 还提供了制造半导体结构的方法。

    Structure of metal e-fuse
    4.
    发明授权
    Structure of metal e-fuse 失效
    金属电熔丝的结构

    公开(公告)号：US08299567B2

    公开(公告)日：2012-10-30

    申请号：US12952317

    申请日：2010-11-23

    申请人： Ping-Chuan Wang ,  Chunyan E Tian ,  Ronald Filippi ,  Wai-kin Li

    发明人： Ping-Chuan Wang ,  Chunyan E Tian ,  Ronald Filippi ,  Wai-kin Li

    IPC分类号： H01L29/00

    CPC分类号： H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Structures of electronic fuses (e-fuse) are provided. An un-programmed e-fuse includes a via of a first conductive material having a bottom and sidewalls with a portion of the sidewalls being covered by a conductive liner and the bottom of the via being formed on top of a dielectric layer, and a first and a second conductive path of a second conductive material formed on top of the dielectric layer with the first and second conductive paths being conductively connected through, and only through, the via at the sidewalls. A programmed e-fuse includes a via; a first conductive path at a first side of the via and being separated from sidewalls of the via by a void; and a second conductive path at a second different side of the via and being in conductive contact with the via through sidewalls of the via.

    摘要翻译： 提供电子保险丝（e-fuse）的结构。 未编程的电子熔断器包括具有底部和侧壁的第一导电材料的通孔，侧壁的一部分被导电衬垫覆盖，并且通孔的底部形成在电介质层的顶部上，并且第一 以及形成在电介质层顶部上的第二导电材料的第二导电路径，其中第一和第二导电路径通过侧壁导通地连接，并且仅通过通孔。 编程的电子熔丝包括通孔; 在通孔的第一侧处的第一导电路径，并且通过空隙与通路的侧壁分离; 以及在所述通孔的第二不同侧的第二导电路径，并且与通孔通过所述通孔的侧壁导电接触。

    Structure of power grid for semiconductor devices and method of making the same
    5.
    发明授权
    Structure of power grid for semiconductor devices and method of making the same 有权
    半导体器件电网结构及其制作方法

    公开(公告)号：US08164190B2

    公开(公告)日：2012-04-24

    申请号：US12491372

    申请日：2009-06-25

    申请人： Ronald Filippi ,  Wai-kin Li ,  Ping-Chuan Wang

    发明人： Ronald Filippi ,  Wai-kin Li ,  Ping-Chuan Wang

    IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40

    CPC分类号： H01L23/5226 ,  H01L21/76802 ,  H01L21/76847 ,  H01L21/76852 ,  H01L23/5286 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53252 ,  H01L23/53266 ,  H01L2924/0002 ,  H01L2924/00

    摘要： An embodiment of the invention provides a semiconductor structure, which may include a stud of a first conductive material formed inside a dielectric layer; a via of a second conductive material having a bottom and sidewalls with the bottom and the sidewalls being covered by a conductive liner, and the bottom being formed directly on top of the stud and being in contact with the via through the conductive liner; and one or more conductive paths of a third conductive material connecting to the via through the conductive liner at the sidewalls of said the. A method of making the semiconductor structure is also provided.

    摘要翻译： 本发明的一个实施例提供一种半导体结构，其可以包括形成在电介质层内部的第一导电材料的支柱; 具有底部的第二导电材料的通孔和具有底部的侧壁，并且侧壁被导电衬垫覆盖，并且底部直接形成在螺柱的顶部上并且通过导电衬套与通孔接触; 以及一个或多个第三导电材料的导电路径，所述第三导电材料在所述导电衬套的侧壁处通过导电衬套连接到通孔。 还提供了制造半导体结构的方法。

    POST CHEMICAL MECHANICAL POLISHING ETCH FOR IMPROVED TIME DEPENDENT DIELECTRIC BREAKDOWN RELIABILITY
    6.
    发明申请
    POST CHEMICAL MECHANICAL POLISHING ETCH FOR IMPROVED TIME DEPENDENT DIELECTRIC BREAKDOWN RELIABILITY 失效
    后期化学机械抛光蚀刻改进时间依赖介质断开可靠性

    公开(公告)号：US20060254053A1

    公开(公告)日：2006-11-16

    申请号：US10908392

    申请日：2005-05-10

    申请人： Kaushik Chanda ,  James Demarest ,  Ronald Filippi ,  Roy Iggulden ,  Edward Kiewra ,  Ping-Chuan Wang ,  Yun-Yu Wang

    发明人： Kaushik Chanda ,  James Demarest ,  Ronald Filippi ,  Roy Iggulden ,  Edward Kiewra ,  Ping-Chuan Wang ,  Yun-Yu Wang

    IPC分类号： H05K3/02 ,  H01K3/10 ,  B24B1/00

    CPC分类号： B24B37/042 ,  H01L21/31144 ,  H01L21/76834 ,  H01L21/7684 ,  H01L21/76849 ,  H01L21/76852 ,  H01L21/76885 ,  Y10T29/49156 ,  Y10T29/49165 ,  Y10T29/49204

    摘要： Disclosed are a damascene and dual damascene processes both of which incorporate the use of a release layer to remove trace amounts of residual material between metal interconnect lines. The release layer is deposited onto a dielectric layer. The release layer comprises an organic material, a dielectric material, a metal or a metal nitride. Trenches are etched into the dielectric layer. The trenches are lined with a liner and filled with a conductor. The conductor and liner materials are polished off the release layer. However, trace amounts of the residual material may remain. The release layer is removed (e.g., by an appropriate solvent or wet etching process) to remove the residual material. If the trench is formed such that the release layer overlaps the walls of the trench, then when the release layer is removed another dielectric layer can be deposited that reinforces the corners around the top of the metal interconnect line.

    摘要翻译： 公开了一种镶嵌和双镶嵌工艺，其中两者都结合使用剥离层以在金属互连线之间移除痕量的残余材料。 释放层沉积在电介质层上。 释放层包括有机材料，电介质材料，金属或金属氮化物。 沟槽蚀刻到电介质层中。 沟槽内衬衬里，填充导体。 导体和衬里材料从剥离层抛光。 然而，痕量的剩余材料可能会残留。 去除脱模层（例如，通过适当的溶剂或湿蚀刻工艺）以除去残留的材料。 如果沟槽形成为使得剥离层与沟槽的壁重叠，则当除去剥离层时，可以沉积另外的介电层，加强围绕金属互连线的顶部的拐角。

    GAS DIELECTRIC STRUCTURE FORMING METHODS
    7.
    发明申请
    GAS DIELECTRIC STRUCTURE FORMING METHODS 失效
    气体电介质结构形成方法

    公开(公告)号：US20060073695A1

    公开(公告)日：2006-04-06

    申请号：US10711697

    申请日：2004-09-30

    申请人： Ronald Filippi ,  Roy Iggulden ,  Edward Kiewra ,  Ping-Chuan Wang

    发明人： Ronald Filippi ,  Roy Iggulden ,  Edward Kiewra ,  Ping-Chuan Wang

    IPC分类号： H01L21/4763 ,  H01L21/311

    CPC分类号： H01L21/7682 ,  H01L21/76807 ,  H01L21/76831 ,  H01L23/5222 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53252 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Methods of forming a gas dielectric structure for a semiconductor structure by using a sacrificial layer. In particular, one embodiment of the invention includes forming an opening for semiconductor structure in a dielectric layer on a substrate; depositing a sacrificial layer over the opening; performing a directional etch on the sacrificial layer to form a sacrificial layer sidewall on the opening; depositing a conductive liner over the opening; depositing a metal in the opening; planarizing the metal and the conductive liner; removing the sacrificial layer sidewall to form a void; and depositing a cap layer over the void to form the gas dielectric structure. The invention is easily implemented in damascene wire formation processes, and improves structural stability.

    摘要翻译： 通过使用牺牲层形成用于半导体结构的气体电介质结构的方法。 特别地，本发明的一个实施例包括在基板上的电介质层中形成用于半导体结构的开口; 在开口上沉积牺牲层; 在所述牺牲层上执行定向蚀刻以在所述开口上形成牺牲层侧壁; 在所述开口上沉积导电衬垫; 在开口中沉积金属; 平面化金属和导电衬垫; 去除牺牲层侧壁以形成空隙; 以及在所述空隙上沉积盖层以形成气体介电结构。 本发明易于在镶嵌线形成过程中实现，并提高结构稳定性。

    CAPACITIVE MONITORS FOR DETECTING METAL EXTRUSION DURING ELECTROMIGRATION
    10.
    发明申请
    CAPACITIVE MONITORS FOR DETECTING METAL EXTRUSION DURING ELECTROMIGRATION 失效
    用于检测电解过程中金属挤压的电容监测器

    公开(公告)号：US20060066314A1

    公开(公告)日：2006-03-30

    申请号：US10711641

    申请日：2004-09-29

    申请人： Ishtiaq Ahsan ,  Ronald Filippi ,  Roy Iggulden ,  Edward Kiewra ,  Ping-Chuan Wang

    发明人： Ishtiaq Ahsan ,  Ronald Filippi ,  Roy Iggulden ,  Edward Kiewra ,  Ping-Chuan Wang

    IPC分类号： G01R31/08

    CPC分类号： H01L22/34 ,  G01R31/2858 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A method and apparatus for detecting metal extrusion associated with electromigration (EM) under high current density situations within an EM test line by measuring changes in capacitance associated with metal extrusion that occurs in the vicinity of the charge carrying surfaces of one or more capacitors situated in locations of close physical proximity to anticipated sites of metal extrusion on an EM test line are provided. The capacitance of each of the one or more capacitors is measured prior to and then during or after operation of the EM test line so as to detect capacitance changes indicating metal extrusion.

    摘要翻译： 一种用于在EM测试线中的高电流密度情况下检测与电迁移（EM）有关的金属挤出的方法和装置，其通过测量在位于一个或多个电容器中的一个或多个电容器的电荷承载表面附近的与金属挤出相关的电容的变化 提供了在EM测试线上与金属挤压的预期位置紧密物理接近的位置。 一个或多个电容器中的每一个的电容在EM测试线之前和之后测量，以便检测指示金属挤压的电容变化。