公开(公告)号：US08349723B2

公开(公告)日：2013-01-08

申请号：US13342221

申请日：2012-01-03

申请人： Ronald Filippi ,  Wai-kin Li ,  Ping-Chuan Wang

发明人： Ronald Filippi ,  Wai-kin Li ,  Ping-Chuan Wang

IPC分类号： H01L21/4763

CPC分类号： H01L23/5226 ,  H01L21/76802 ,  H01L21/76847 ,  H01L21/76852 ,  H01L23/5286 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53252 ,  H01L23/53266 ,  H01L2924/0002 ,  H01L2924/00

摘要： An embodiment of the invention provides a semiconductor structure, which may include a stud of a first conductive material formed inside a dielectric layer; a via of a second conductive material having a bottom and sidewalls with the bottom and the sidewalls being covered by a conductive liner, and the bottom being formed directly on top of the stud and being in contact with the via through the conductive liner; and one or more conductive paths of a third conductive material connecting to the via through the conductive liner at the sidewalls of said the. A method of making the semiconductor structure is also provided.

摘要翻译： 本发明的一个实施例提供一种半导体结构，其可以包括形成在电介质层内部的第一导电材料的支柱; 具有底部的第二导电材料的通孔和具有底部的侧壁，并且侧壁被导电衬垫覆盖，并且底部直接形成在螺柱的顶部上并且通过导电衬套与通孔接触; 以及一个或多个第三导电材料的导电路径，所述第三导电材料在所述导电衬套的侧壁处通过所述导电衬套连接到所述通孔。 还提供了制造半导体结构的方法。

公开(公告)号：US08299567B2

公开(公告)日：2012-10-30

申请号：US12952317

申请日：2010-11-23

申请人： Ping-Chuan Wang ,  Chunyan E Tian ,  Ronald Filippi ,  Wai-kin Li

发明人： Ping-Chuan Wang ,  Chunyan E Tian ,  Ronald Filippi ,  Wai-kin Li

IPC分类号： H01L29/00

CPC分类号： H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

摘要： Structures of electronic fuses (e-fuse) are provided. An un-programmed e-fuse includes a via of a first conductive material having a bottom and sidewalls with a portion of the sidewalls being covered by a conductive liner and the bottom of the via being formed on top of a dielectric layer, and a first and a second conductive path of a second conductive material formed on top of the dielectric layer with the first and second conductive paths being conductively connected through, and only through, the via at the sidewalls. A programmed e-fuse includes a via; a first conductive path at a first side of the via and being separated from sidewalls of the via by a void; and a second conductive path at a second different side of the via and being in conductive contact with the via through sidewalls of the via.

摘要翻译： 提供电子保险丝（e-fuse）的结构。 未编程的电子熔断器包括具有底部和侧壁的第一导电材料的通孔，侧壁的一部分被导电衬垫覆盖，并且通孔的底部形成在电介质层的顶部上，并且第一 以及形成在电介质层顶部上的第二导电材料的第二导电路径，其中第一和第二导电路径通过侧壁导通地连接，并且仅通过通孔。 编程的电子熔丝包括通孔; 在通孔的第一侧处的第一导电路径，并且通过空隙与通路的侧壁分离; 以及在所述通孔的第二不同侧的第二导电路径，并且与通孔通过所述通孔的侧壁导电接触。

公开(公告)号：US08164190B2

公开(公告)日：2012-04-24

申请号：US12491372

申请日：2009-06-25

申请人： Ronald Filippi ,  Wai-kin Li ,  Ping-Chuan Wang

发明人： Ronald Filippi ,  Wai-kin Li ,  Ping-Chuan Wang

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L23/5226 ,  H01L21/76802 ,  H01L21/76847 ,  H01L21/76852 ,  H01L23/5286 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53252 ,  H01L23/53266 ,  H01L2924/0002 ,  H01L2924/00

摘要： An embodiment of the invention provides a semiconductor structure, which may include a stud of a first conductive material formed inside a dielectric layer; a via of a second conductive material having a bottom and sidewalls with the bottom and the sidewalls being covered by a conductive liner, and the bottom being formed directly on top of the stud and being in contact with the via through the conductive liner; and one or more conductive paths of a third conductive material connecting to the via through the conductive liner at the sidewalls of said the. A method of making the semiconductor structure is also provided.

摘要翻译： 本发明的一个实施例提供一种半导体结构，其可以包括形成在电介质层内部的第一导电材料的支柱; 具有底部的第二导电材料的通孔和具有底部的侧壁，并且侧壁被导电衬垫覆盖，并且底部直接形成在螺柱的顶部上并且通过导电衬套与通孔接触; 以及一个或多个第三导电材料的导电路径，所述第三导电材料在所述导电衬套的侧壁处通过导电衬套连接到通孔。 还提供了制造半导体结构的方法。

公开(公告)号：US20100327445A1

公开(公告)日：2010-12-30

申请号：US12491372

申请日：2009-06-25

申请人： Ronald Filippi ,  Wai-kin Li ,  Ping-Chuan Wang

发明人： Ronald Filippi ,  Wai-kin Li ,  Ping-Chuan Wang

IPC分类号： H01L23/535 ,  H01L21/768

CPC分类号： H01L23/5226 ,  H01L21/76802 ,  H01L21/76847 ,  H01L21/76852 ,  H01L23/5286 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53252 ,  H01L23/53266 ,  H01L2924/0002 ,  H01L2924/00

摘要： An embodiment of the invention provides a semiconductor structure, which may include a stud of a first conductive material formed inside a dielectric layer; a via of a second conductive material having a bottom and sidewalls with the bottom and the sidewalls being covered by a conductive liner, and the bottom being formed directly on top of the stud and being in contact with the via through the conductive liner; and one or more conductive paths of a third conductive material connecting to the via through the conductive liner at the sidewalls of said the. A method of making the semiconductor structure is also provided.

摘要翻译： 本发明的一个实施例提供一种半导体结构，其可以包括形成在电介质层内部的第一导电材料的支柱; 具有底部的第二导电材料的通孔和具有底部的侧壁，并且侧壁被导电衬垫覆盖，并且底部直接形成在螺柱的顶部上并且通过导电衬套与通孔接触; 以及一个或多个第三导电材料的导电路径，所述第三导电材料在所述导电衬套的侧壁处通过所述导电衬套连接到所述通孔。 还提供了制造半导体结构的方法。

公开(公告)号：US20120100712A1

公开(公告)日：2012-04-26

申请号：US13342221

申请日：2012-01-03

申请人： Ronald Filippi ,  Wai-kin Li ,  Ping-Chuan Wang

发明人： Ronald Filippi ,  Wai-kin Li ,  Ping-Chuan Wang

IPC分类号： H01L21/76

CPC分类号： H01L23/5226 ,  H01L21/76802 ,  H01L21/76847 ,  H01L21/76852 ,  H01L23/5286 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53252 ,  H01L23/53266 ,  H01L2924/0002 ,  H01L2924/00

摘要： An embodiment of the invention provides a semiconductor structure, which may include a stud of a first conductive material formed inside a dielectric layer; a via of a second conductive material having a bottom and sidewalls with the bottom and the sidewalls being covered by a conductive liner, and the bottom being formed directly on top of the stud and being in contact with the via through the conductive liner; and one or more conductive paths of a third conductive material connecting to the via through the conductive liner at the sidewalls of said the. A method of making the semiconductor structure is also provided.

摘要翻译： 本发明的一个实施例提供一种半导体结构，其可以包括形成在电介质层内部的第一导电材料的支柱; 具有底部的第二导电材料的通孔和具有底部的侧壁，并且侧壁被导电衬垫覆盖，并且底部直接形成在螺柱的顶部上并且通过导电衬套与通孔接触; 以及一个或多个第三导电材料的导电路径，所述第三导电材料在所述导电衬套的侧壁处通过所述导电衬套连接到所述通孔。 还提供了制造半导体结构的方法。

公开(公告)号：US08158014B2

公开(公告)日：2012-04-17

申请号：US12139722

申请日：2008-06-16

申请人： Wu-Song Huang ,  Wai-kin Li ,  Ping-Chuan Wang

发明人： Wu-Song Huang ,  Wai-kin Li ,  Ping-Chuan Wang

IPC分类号： C03C15/00 ,  H01L21/31

CPC分类号： G03F7/70466 ,  Y10S438/947 ,  Y10S438/948 ,  Y10T428/24802

摘要： A stack of a second photoresist having a second photosensitivity and a first photoresist having a first photosensitivity, which is greater than second photosensitivity, is formed on a substrate. A first pattern is formed in the first photoresist by a first exposure and a first development, while the second photoresist underneath remains intact. A second pattern comprising an array of lines is formed in the second photoresist. An exposed portion of the second photoresist underneath a remaining portion of the first photoresist forms a narrow portion of a line pattern, while an exposed portion of the second photoresist outside the area of the remaining portions of the photoresist forms a wide portion of the line pattern. Each wide portion of the line pattern forms a bulge in the second pattern, which increases overlay tolerance between the second pattern and the pattern of conductive vias.

摘要翻译： 在基板上形成具有第二感光性的第二光致抗蚀剂的叠层和具有大于第二光敏性的第一光敏性的第一光致抗蚀剂。 通过第一曝光和第一显影在第一光致抗蚀剂中形成第一图案，而下面的第二光致抗蚀剂保持完整。 在第二光致抗蚀剂中形成包括线阵列的第二图案。 在第一光致抗蚀剂的剩余部分下面的第二光致抗蚀剂的暴露部分形成线图案的窄部分，而在光致抗蚀剂的剩余部分的区域外部的第二光致抗蚀剂的暴露部分形成线图案的宽部分 。 线图案的每个宽部分在第二图案中形成凸起，这增加了第二图案和导电通孔图案之间的覆盖公差。

公开(公告)号：US20090311491A1

公开(公告)日：2009-12-17

申请号：US12139722

申请日：2008-06-16

申请人： Wu-Song Huang ,  Wai-kin Li ,  Ping-Chuan Wang

发明人： Wu-Song Huang ,  Wai-kin Li ,  Ping-Chuan Wang

IPC分类号： G03F7/20 ,  B32B5/00

CPC分类号： G03F7/70466 ,  Y10S438/947 ,  Y10S438/948 ,  Y10T428/24802

摘要： A stack of a second photoresist having a second photosensitivity and a first photoresist having a first photosensitivity, which is greater than second photosensitivity, is formed on a substrate. A first pattern is formed in the first photoresist by a first exposure and a first development, while the second photoresist underneath remains intact. A second pattern comprising an array of lines is formed in the second photoresist. An exposed portion of the second photoresist underneath a remaining portion of the first photoresist forms a narrow portion of a line pattern, while an exposed portion of the second photoresist outside the area of the remaining portions of the photoresist forms a wide portion of the line pattern. Each wide portion of the line pattern forms a bulge in the second pattern, which increases overlay tolerance between the second pattern and the pattern of conductive vias.

摘要翻译： 在基板上形成具有第二感光性的第二光致抗蚀剂的叠层和具有大于第二光敏性的第一光敏性的第一光致抗蚀剂。 通过第一曝光和第一显影在第一光致抗蚀剂中形成第一图案，而下面的第二光致抗蚀剂保持完整。 在第二光致抗蚀剂中形成包括线阵列的第二图案。 在第一光致抗蚀剂的剩余部分下面的第二光致抗蚀剂的暴露部分形成线图案的窄部分，而在光致抗蚀剂的剩余部分的区域外部的第二光致抗蚀剂的暴露部分形成线图案的宽部分 。 线图案的每个宽部分在第二图案中形成凸起，这增加了第二图案和导电通孔图案之间的覆盖公差。

公开(公告)号：US20120156450A1

公开(公告)日：2012-06-21

申请号：US13406965

申请日：2012-02-28

申请人： Wu-Song Huang ,  Wai-kin Li ,  Ping-Chuan Wang

发明人： Wu-Song Huang ,  Wai-kin Li ,  Ping-Chuan Wang

IPC分类号： B32B3/00

CPC分类号： G03F7/70466 ,  Y10S438/947 ,  Y10S438/948 ,  Y10T428/24802

摘要： A stack of a second photoresist having a second photosensitivity and a first photoresist having a first photosensitivity, which is greater than second photosensitivity, is formed on a substrate. A first pattern is formed in the first photoresist by a first exposure and a first development, while the second photoresist underneath remains intact. A second pattern comprising an array of lines is formed in the second photoresist. An exposed portion of the second photoresist underneath a remaining portion of the first photoresist forms a narrow portion of a line pattern, while an exposed portion of the second photoresist outside the area of the remaining portions of the photoresist forms a wide portion of the line pattern. Each wide portion of the line pattern forms a bulge in the second pattern, which increases overlay tolerance between the second pattern and the pattern of conductive vias.

摘要翻译： 在基板上形成具有第二感光性的第二光致抗蚀剂的叠层和具有大于第二光敏性的第一光敏性的第一光致抗蚀剂。 通过第一曝光和第一显影在第一光致抗蚀剂中形成第一图案，而下面的第二光致抗蚀剂保持完整。 在第二光致抗蚀剂中形成包括线阵列的第二图案。 在第一光致抗蚀剂的剩余部分下面的第二光致抗蚀剂的暴露部分形成线图案的窄部分，而在光致抗蚀剂的剩余部分的区域外的第二光致抗蚀剂的暴露部分形成线图案的宽部分 。 线图案的每个宽部分在第二图案中形成凸起，这增加了第二图案和导电通孔图案之间的覆盖公差。

公开(公告)号：US07696085B2

公开(公告)日：2010-04-13

申请号：US12034122

申请日：2008-02-20

申请人： Wai-kin Li ,  Haining S. Yang

发明人： Wai-kin Li ,  Haining S. Yang

IPC分类号： H01L21/4763

CPC分类号： H01L21/31144 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/76811 ,  H01L21/76813 ,  H01L21/76816

摘要： A recessed region containing a line portion and a bulge portion is formed in a hard mask layer. Self-assembling block copolymers containing two or more different polymeric block components that are immiscible with one another are applied within the recessed region and annealed. A cylindrical polymeric block centered at the bulge portion is removed selective to a polymeric block matrix surrounding the cylindrical polymeric block. A via cavity is formed by transferring the cavity formed by removal of the cylindrical polymeric block into a dielectric layer. The pattern in the hard mask layer is subsequently transferred into the dielectric layer to form a line cavity. A metal via and a metal line are formed by deposition and planarization of metal. The metal via is self-aligned to the metal line.

摘要翻译： 在硬掩模层中形成包含线部分和凸起部分的凹陷区域。 包含彼此不混溶的两种或更多种不同的聚合物嵌段组分的自组装嵌段共聚物被施加在凹陷区域内并退火。 以凸出部分为中心的圆柱形聚合物块被选择性地除去围绕圆柱形聚合物嵌段的聚合物嵌段基体。 通过将通过将圆柱形聚合物块除去形成的空腔转移到电介质层中而形成通孔。 随后将硬掩模层中的图案转移到电介质层中以形成线腔。 通过金属的沉积和平坦化形成金属通孔和金属线。 金属通孔与金属线自对准。

公开(公告)号：US20090085151A1

公开(公告)日：2009-04-02

申请号：US11863814

申请日：2007-09-28

申请人： Deok-kee Kim ,  Wai-kin Li ,  Haining Sam Yang

发明人： Deok-kee Kim ,  Wai-kin Li ,  Haining Sam Yang

IPC分类号： H01L29/40 ,  H01L21/44

CPC分类号： H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

摘要： An electrical structure and method of forming. The electrical structure includes a semiconductor substrate, an insulator layer formed over and in contact with the semiconductor substrate, and a semiconductor fuse structure formed over the insulator layer. The fuse structure includes a silicon layer and a continuous metallic silicide layer. The continuous metallic silicide layer includes a first section formed over and in contact with a first horizontal section of a top surface of the silicon layer, a second section formed over and in contact with a second horizontal section of the top surface of the silicon layer, and a third section formed within an opening within the top surface of the silicon layer.

摘要翻译： 一种电气结构和成型方法。 电结构包括半导体衬底，形成在半导体衬底上并与半导体衬底接触的绝缘体层，以及形成在绝缘体层上的半导体熔丝结构。 熔丝结构包括硅层和连续的金属硅化物层。 连续金属硅化物层包括形成在硅层的顶表面的第一水平部分上并与其接触的第一部分，形成在硅层的顶表面的第二水平部分上并与其接触的第二部分， 以及形成在所述硅层的顶表面内的开口内的第三部分。