公开(公告)号：US20080224135A1

公开(公告)日：2008-09-18

申请号：US12128260

申请日：2008-05-28

申请人： Ronald Gene Filippi ,  Jason Paul Gill ,  Vincent J. McGahay ,  Paul Stephen McLaughlin ,  Hazara Singh Rathore ,  Thomas M. Shaw ,  Ping-Chuan Wang ,  Conal Eugene Murray

发明人： Ronald Gene Filippi ,  Jason Paul Gill ,  Vincent J. McGahay ,  Paul Stephen McLaughlin ,  Hazara Singh Rathore ,  Thomas M. Shaw ,  Ping-Chuan Wang ,  Conal Eugene Murray

IPC分类号： H01L23/58

CPC分类号： H01L22/34 ,  H01L22/32 ,  H01L23/5226 ,  H01L23/562 ,  H01L2924/0002 ,  H05K1/0268 ,  H05K1/0269 ,  H05K1/092 ,  Y10S438/927 ,  Y10T29/49004 ,  H01L2924/00

摘要： A device and method for evaluating reliability of a semiconductor chip structure built by a manufacturing process includes a test structure built in accordance with a manufacturing process. The test structure is thermal cycled and the yield of the test structure is measured. The reliability of the semiconductor chip structure built by the manufacturing process is evaluated based on the yield performance before the thermal cycling.

摘要翻译： 用于评估通过制造工艺构建的半导体芯片结构的可靠性的装置和方法包括根据制造过程构建的测试结构。 测试结构热循环，测量结构的产量。 基于在热循环之前的产量性能来评估由制造工艺构建的半导体芯片结构的可靠性。

公开(公告)号：US07388224B2

公开(公告)日：2008-06-17

申请号：US11502196

申请日：2006-08-10

申请人： Ronald Gene Filippi ,  Jason Paul Gill ,  Vincent J. McGahay ,  Paul Stephen McLaughlin ,  Conal Eugene Murray ,  Hazara Singh Rathore ,  Thomas M. Shaw ,  Ping-Chuan Wang

发明人： Ronald Gene Filippi ,  Jason Paul Gill ,  Vincent J. McGahay ,  Paul Stephen McLaughlin ,  Conal Eugene Murray ,  Hazara Singh Rathore ,  Thomas M. Shaw ,  Ping-Chuan Wang

IPC分类号： H01L23/58

CPC分类号： H01L22/34 ,  H01L22/32 ,  H01L23/5226 ,  H01L23/562 ,  H01L2924/0002 ,  H05K1/0268 ,  H05K1/0269 ,  H05K1/092 ,  Y10S438/927 ,  Y10T29/49004 ,  H01L2924/00

摘要： A device and method for evaluating reliability of a semiconductor chip structure built by a manufacturing process includes a test structure built in accordance with a manufacturing process. The test structure is thermal cycled and the yield of the test structure is measured. The reliability of the semiconductor chip structure built by the manufacturing process is evaluated based on the yield performance before the thermal cycling.

摘要翻译： 用于评估通过制造工艺构建的半导体芯片结构的可靠性的装置和方法包括根据制造过程构建的测试结构。 测试结构热循环，测量结构的产量。 基于在热循环之前的产量性能来评估由制造工艺构建的半导体芯片结构的可靠性。

公开(公告)号：US07098054B2

公开(公告)日：2006-08-29

申请号：US10783462

申请日：2004-02-20

申请人： Ronald Gene Filippi ,  Jason Paul Gill ,  Vincent J. McGahay ,  Paul Stephen McLaughlin ,  Conal Eugene Murray ,  Hazara Singh Rathore ,  Thomas M. Shaw ,  Ping-Chuan Wang

发明人： Ronald Gene Filippi ,  Jason Paul Gill ,  Vincent J. McGahay ,  Paul Stephen McLaughlin ,  Conal Eugene Murray ,  Hazara Singh Rathore ,  Thomas M. Shaw ,  Ping-Chuan Wang

IPC分类号： H01L21/66

CPC分类号： H01L22/34 ,  H01L22/32 ,  H01L23/5226 ,  H01L23/562 ,  H01L2924/0002 ,  H05K1/0268 ,  H05K1/0269 ,  H05K1/092 ,  Y10S438/927 ,  Y10T29/49004 ,  H01L2924/00

摘要： A device and method for evaluating reliability of a semiconductor chip structure built by a manufacturing process includes a test structure built in accordance with a manufacturing process. The test structure is thermal cycled and the yield of the test structure is measured. The reliability of the semiconductor chip structure built by the manufacturing process is evaluated based on the yield performance before the thermal cycling.

公开(公告)号：US09287186B2

公开(公告)日：2016-03-15

申请号：US12128260

申请日：2008-05-28

申请人： Ronald Gene Filippi ,  Jason Paul Gill ,  Vincent J. McGahay ,  Paul Stephen McLaughlin ,  Conal Eugene Murray ,  Hazara Singh Rathore ,  Thomas M. Shaw ,  Ping-Chuan Wang

发明人： Ronald Gene Filippi ,  Jason Paul Gill ,  Vincent J. McGahay ,  Paul Stephen McLaughlin ,  Conal Eugene Murray ,  Hazara Singh Rathore ,  Thomas M. Shaw ,  Ping-Chuan Wang

IPC分类号： H01L23/58 ,  H01L21/66 ,  H01L23/522 ,  H01L23/00 ,  H05K1/09 ,  H05K1/02

CPC分类号： H01L22/34 ,  H01L22/32 ,  H01L23/5226 ,  H01L23/562 ,  H01L2924/0002 ,  H05K1/0268 ,  H05K1/0269 ,  H05K1/092 ,  Y10S438/927 ,  Y10T29/49004 ,  H01L2924/00

摘要： A device and method for evaluating reliability of a semiconductor chip structure built by a manufacturing process includes a test structure built in accordance with a manufacturing process. The test structure is thermal cycled and the yield of the test structure is measured. The reliability of the semiconductor chip structure built by the manufacturing process is evaluated based on the yield performance before the thermal cycling.

公开(公告)号：US07345305B2

公开(公告)日：2008-03-18

申请号：US11248719

申请日：2005-10-12

申请人： Ronald Gene Filippi ,  Lynne Marie Gignac ,  Vincent J. McGahay ,  Conal Eugene Murray ,  Hazara Singh Rathore ,  Thomas M. Shaw ,  Ping-Chuan Wang

发明人： Ronald Gene Filippi ,  Lynne Marie Gignac ,  Vincent J. McGahay ,  Conal Eugene Murray ,  Hazara Singh Rathore ,  Thomas M. Shaw ,  Ping-Chuan Wang

IPC分类号： H01L23/58

CPC分类号： G01R31/2881

摘要： A device, system and method for evaluating reliability of a semiconductor chip are disclosed. Strain is determined at a location of interest in a structure. Failures are evaluated in a plurality of the structures after stress cycling to determine a strain threshold with respect to a feature characteristic. Structures on a chip or chips are evaluated based on the feature characteristic to predict reliability based on the strain threshold and the feature characteristic. Predictions and design changes may be made based on the results.

摘要翻译： 公开了一种用于评估半导体芯片的可靠性的装置，系统和方法。 在结构中感兴趣的位置确定菌株。 在应力循环之后，在多个结构中评估失效以确定关于特征特征的应变阈值。 基于特征特征评估芯片或芯片上的结构，以基于应变阈值和特征特征来预测可靠性。 可以根据结果进行预测和设计更改。

公开(公告)号：US06989282B2

公开(公告)日：2006-01-24

申请号：US10815418

申请日：2004-04-01

申请人： Ronald Gene Filippi ,  Lynne Marie Gignac ,  Vincent J. McGahay ,  Conal Eugene Murray ,  Hazara Singh Rathore ,  Thomas M. Shaw ,  Ping-Chuan Wang

发明人： Ronald Gene Filippi ,  Lynne Marie Gignac ,  Vincent J. McGahay ,  Conal Eugene Murray ,  Hazara Singh Rathore ,  Thomas M. Shaw ,  Ping-Chuan Wang

IPC分类号： H01L21/66

CPC分类号： G01R31/2881

摘要： A device, system and method for evaluating reliability of a semiconductor chip are disclosed. Strain is determined at a location of interest in a structure. Failures are evaluated in a plurality of the structures after stress cycling to determine a strain threshold with respect to a feature characteristic. Structures on a chip or chips are evaluated based on the feature characteristic to predict reliability based on the strain threshold and the feature characteristic. Predictions and design changes may be made based on the results.

摘要翻译： 公开了一种用于评估半导体芯片的可靠性的装置，系统和方法。 在结构中感兴趣的位置确定菌株。 在应力循环之后，在多个结构中评估失效以确定关于特征特征的应变阈值。 基于特征特征评估芯片或芯片上的结构，以基于应变阈值和特征特征来预测可靠性。 可以根据结果进行预测和设计更改。

公开(公告)号：US07119545B2

公开(公告)日：2006-10-10

申请号：US10711641

申请日：2004-09-29

申请人： Ishtiaq Ahsan ,  Ronald Gene Filippi ,  Roy Charles Iggulden ,  Edward William Kiewra ,  Ping-Chuan Wang

发明人： Ishtiaq Ahsan ,  Ronald Gene Filippi ,  Roy Charles Iggulden ,  Edward William Kiewra ,  Ping-Chuan Wang

IPC分类号： G01R31/08 ,  G01R27/26

CPC分类号： H01L22/34 ,  G01R31/2858 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method and apparatus for detecting metal extrusion associated with electromigration (EM) under high current density situations within an EM test line by measuring changes in capacitance associated with metal extrusion that occurs in the vicinity of the charge carrying surfaces of one or more capacitors situated in locations of close physical proximity to anticipated sites of metal extrusion on an EM test line are provided. The capacitance of each of the one or more capacitors is measured prior to and then during or after operation of the EM test line so as to detect capacitance changes indicating metal extrusion.

摘要翻译： 一种用于在EM测试线中的高电流密度情况下检测与电迁移（EM）有关的金属挤出的方法和装置，其通过测量在位于一个或多个电容器中的一个或多个电容器的电荷承载表面附近的与金属挤出相关的电容的变化 提供了在EM测试线上与金属挤压的预期位置紧密物理接近的位置。 一个或多个电容器中的每一个的电容在EM测试线之前和之后测量，以便检测指示金属挤压的电容变化。

公开(公告)号：US07473636B2

公开(公告)日：2009-01-06

申请号：US11306825

申请日：2006-01-12

申请人： Kaushik Chanda ,  James J. Demarest ,  Ronald G. Filippi ,  Roy C. Iggulden ,  Edward W. Kiewra ,  Vincent J. McGahay ,  Ping-Chuan Wang ,  Yun-Yu Wang

发明人： Kaushik Chanda ,  James J. Demarest ,  Ronald G. Filippi ,  Roy C. Iggulden ,  Edward W. Kiewra ,  Vincent J. McGahay ,  Ping-Chuan Wang ,  Yun-Yu Wang

IPC分类号： H01L21/4763

CPC分类号： H01L23/53238 ,  H01L21/76846 ,  H01L23/5283 ,  H01L2924/0002 ,  H01L2924/00

摘要： In the back end of an integrated circuit employing dual-damascene interconnects, the interconnect members have a first non-conformal liner that has a thicker portion at the top of the trench level of the interconnect; and a conformal second liner that combines with the first liner to block diffusion of the metal fill material.

摘要翻译： 在采用双镶嵌互连的集成电路的后端中，互连构件具有第一非保形衬套，其在互连的沟槽级的顶部具有较厚的部分; 以及与第一衬垫结合以阻挡金属填充材料的扩散的共形第二衬垫。

公开(公告)号：US08853693B2

公开(公告)日：2014-10-07

申请号：US13423823

申请日：2012-03-19

申请人： Hanyi Ding ,  Kai D. Feng ,  Ping-Chuan Wang ,  Zhijian Yang

发明人： Hanyi Ding ,  Kai D. Feng ,  Ping-Chuan Wang ,  Zhijian Yang

IPC分类号： H01L21/00 ,  H01L21/768 ,  H01L21/66

CPC分类号： H01L22/34 ,  H01L21/76898

摘要： A test structure for a through-silicon-via (TSV) in a semiconductor chip includes a first contact, the first contact being electrically connected to a first TSV; and a second contact, wherein the first contact, second contact, and the first TSV form a first channel, and a depth of the first TSV is determined based on a resistance of the first channel.

摘要翻译： 半导体芯片中的贯穿硅通孔（TSV）的测试结构包括：第一触点，第一触点电连接到第一TSV; 以及第二触点，其中所述第一触点，所述第二触点和所述第一TSV形成第一通道，并且基于所述第一通道的电阻来确定所述第一TSV的深度。

公开(公告)号：US08450205B2

公开(公告)日：2013-05-28

申请号：US13474244

申请日：2012-05-17

申请人： Louis L. Hsu ,  Conal E. Murray ,  Ping-Chuan Wang ,  Chih-Chao Yang

发明人： Louis L. Hsu ,  Conal E. Murray ,  Ping-Chuan Wang ,  Chih-Chao Yang

IPC分类号： H01L21/4763

CPC分类号： H01L21/76816 ,  H01L21/76838 ,  H01L21/76847 ,  H01L23/5226 ,  H01L23/528 ,  H01L2924/0002 ,  H01L2924/00

摘要： An IC interconnect for high direct current (DC) that is substantially immune to electro-migration (EM) damage, and a method of manufacture of the IC interconnect are provided. A structure includes a cluster-of-via structure at an intersection between inter-level wires. The cluster-of-via structure includes a plurality of vias each of which are filled with a metal and lined with a liner material. At least two adjacent of the vias are in contact with one another and the plurality of vias lowers current loading between the inter-level wires.

摘要翻译： 提供了基本上不受电迁移（EM）损害的高直流（DC）的IC互连以及IC互连的制造方法。 一种结构包括层间电线之间的交叉处的通孔簇结构。 通孔结构包括多个通孔，每个通孔填充有金属并衬有衬垫材料。 至少两个相邻的通孔彼此接触并且多个通孔降低了层间电线之间的电流负载。