公开(公告)号：US5343432A

公开(公告)日：1994-08-30

申请号：US669725

申请日：1991-03-14

申请人： Ryuichi Matsuo ,  Ryuichi Kosugi ,  Nobuhiro Tsuda ,  Osamu Ishizaki

发明人： Ryuichi Matsuo ,  Ryuichi Kosugi ,  Nobuhiro Tsuda ,  Osamu Ishizaki

IPC分类号： G11C11/41 ,  G11C7/12 ,  G11C8/18 ,  G11C7/00 ,  G11C8/00

CPC分类号： G11C7/12 ,  G11C8/18

摘要： A semiconductor memory device includes an array of memory cells arranged in rows and columns; a plurality of word lines connected to the rows of the memory cells; a plurality of bit lines connected to the columns of the memory cells; word line selection means; bit line selection means; and equalizing means for equalizing the bit line to a desired voltage level in response to an address signal, and for terminating the equalization in response to change in a signal on a word line according to change in the address signal.

摘要翻译： 半导体存储器件包括排列成行和列的存储单元阵列; 连接到存储器单元的行的多个字线; 连接到存储器单元的列的多个位线; 字线选择手段; 位线选择手段; 以及均衡装置，用于响应于地址信号将位线均衡到期望的电压电平，并且响应于根据地址信号的变化在字线上的信号的变化来终止均衡。

公开(公告)号：US5666324A

公开(公告)日：1997-09-09

申请号：US616386

申请日：1996-03-15

申请人： Ryuichi Kosugi ,  Shigeki Ohbayashi

发明人： Ryuichi Kosugi ,  Shigeki Ohbayashi

IPC分类号： G11C7/10 ,  G11C7/22 ,  G11C8/00

CPC分类号： G11C7/22 ,  G11C7/1072

摘要： A synchronous semiconductor memory device includes a clock pulse generator generating internal first and second clock pulses in synchronization with an external clock signal for application, respectively, to a word line select decoder selecting a row of memory cells, and to a bit line select decoder selecting a column of memory cells, a sense amplifier sensing and amplifying a data of selected memory cell and a write driver writing a data to the selected memory cell. Word line select decoder is enabled when the first clock pulse is active, and bit line select decoder, sense amplifier and write driver are activated when the second clock pulse is active. These circuits are activated only for a necessary minimum period, and current consumption is reduced.

摘要翻译： 同步半导体存储器件包括时钟脉冲发生器，分别产生与应用的外部时钟信号同步的内部第一和第二时钟脉冲到选择一行存储器单元的字线选择解码器，以及位线选择解码器选择 一列存储单元，一个感测放大器，用于感测和放大所选存储单元的数据，以及一写入驱动器将数据写入所选存储单元。 当第一个时钟脉冲有效时，字线选择解码器被使能，当第二个时钟脉冲有效时，位线选择解码器，读出放大器和写入驱动器被激活。 这些电路仅在必要的最小周期被激活，并且电流消耗被降低。

公开(公告)号：US06351433B1

公开(公告)日：2002-02-26

申请号：US09549344

申请日：2000-04-13

申请人： Ryuichi Kosugi

发明人： Ryuichi Kosugi

IPC分类号： G11C800

CPC分类号： G11C7/109 ,  G11C7/1039 ,  G11C7/1051 ,  G11C7/1078 ,  G11C7/1087 ,  G11C7/1093 ,  G11C8/00

摘要： A synchronous semiconductor memory device according to the present invention includes a memory array circuit for performing reading/writing of data sent to or received at a data terminal with respect to a memory cell array; a write data retaining circuit and a write address retaining circuit for temporarily retaining write data and addresses corresponding to the write data, respectively; an address matching circuit for performing matching of an input address with addresses stored in the address retaining circuit; and a data path select circuit for outputting the write data temporarily stored in the write data retaining circuit to the data terminal according to the matching result. The address matching circuit is disabled during a clock cycle in which a writing operation is designated.

摘要翻译： 根据本发明的同步半导体存储器件包括：存储器阵列电路，用于对存储单元阵列执行数据终端发送或接收的数据的读/写; 写入数据保持电路和写入地址保持电路，用于分别暂时保留对应于写入数据的写入数据和地址; 地址匹配电路，用于执行输入地址与存储在地址保持电路中的地址的匹配; 以及数据路径选择电路，用于根据匹配结果将临时存储在写入数据保持电路中的写入数据输出到数据终端。 地址匹配电路在指定写入操作的时钟周期内被禁止。

公开(公告)号：US06582085B2

公开(公告)日：2003-06-24

申请号：US09988178

申请日：2001-11-19

申请人： Ryuichi Kosugi

发明人： Ryuichi Kosugi

IPC分类号： H01L2358

CPC分类号： H01L22/34 ,  H01L2224/48091 ,  H01L2924/00014

摘要： A silicon wafer has a plurality of chip portions and a plurality of street portions. Each of the street portions runs and spaces between neighboring chip portions. The wafer also has circuits each provided on the street portions. The circuit is reinforced by a reinforcing portion. The reinforcing portion is provided on the circuit before dicing and then cut out in part by dicing so that it remains in part on at least one end portion of the circuit, adjacent to the chip portions, after dicing.

摘要翻译： 硅晶片具有多个芯片部分和多个街道部分。 每个街道部分在相邻的芯片部分之间延伸和间隔。 晶片还具有各自设置在街道部分上的电路。 电路由加强部分加强。 加强部分在切割之前设置在电路上，然后通过切割部分地切割，使得其在切割之后部分保留在与芯片部分相邻的电路的至少一个端部。

公开(公告)号：US06559489B2

公开(公告)日：2003-05-06

申请号：US09544983

申请日：2000-04-07

申请人： Ryuichi Kosugi ,  Shigeki Ohbayashi

发明人： Ryuichi Kosugi ,  Shigeki Ohbayashi

IPC分类号： H01L2972

CPC分类号： H01L21/76802 ,  H01L21/28512 ,  H01L21/76877 ,  H01L21/823475

摘要： A semiconductor device capable of a high-speed operation is provided. The semiconductor device is provided with low concentration impurity regions, a gate electrode formed with gate oxide film interposed between the gate electrode and a silicon substrate, an etching stopper, an interlayer insulating film having a contact hole and having an etching rate greater than that of the etching stopper, a high concentration impurity region formed by implanting an impurity into the silicon substrate through the contact hole, a plug layer filling the contact hole, and an interconnection layer.

公开(公告)号：US4958322A

公开(公告)日：1990-09-18

申请号：US376067

申请日：1989-07-06

申请人： Ryuichi Kosugi ,  Tsugio Tabaru

发明人： Ryuichi Kosugi ,  Tsugio Tabaru

IPC分类号： G11C11/403 ,  G11C5/00 ,  G11C7/00 ,  G11C11/40 ,  G11C11/401 ,  H01L27/10 ,  H05K1/14 ,  H05K1/18 ,  H05K3/46

CPC分类号： G11C5/00 ,  G11C11/40 ,  H05K1/141 ,  H05K1/181

摘要： A semiconductor pseudo memory module includes a multilayer wiring substrate on the surface of which a plurality of DRAMs are provided and on the reverse side of which semiconductor devices of the DRAM controller and multiplexers are provided, these devices being electrically connectetd with one another by a wiring layer. The address signals supplied from outside are converted into column address signals and row address signals by the multiplexer so as to be supplied to each DRAM. Responsive to control signals supplied from outside, the DRAM controller generates a refresh signals for refreshing the DRAMS, which signal is supplied to the DRAM. In this manner, the DRAM may be used as the SRAM.

摘要翻译： 半导体伪存储器模块包括其表面上设置有多个DRAM的多层布线基板，并且在其背面设置有DRAM控制器和多路复用器的半导体器件，这些器件通过布线彼此电连接 层。 从外部提供的地址信号由多路复用器转换为列地址信号和行地址信号，以便提供给每个DRAM。 响应于从外部提供的控制信号，DRAM控制器产生用于刷新DRAMS的刷新信号，该信号被提供给DRAM。 以这种方式，DRAM可以用作SRAM。