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    Semiconductor inspection apparatus
    6.
    发明授权
    Semiconductor inspection apparatus 失效
    半导体检测仪器

    公开(公告)号：US06714030B2

    公开(公告)日：2004-03-30

    申请号：US10390412

    申请日：2003-03-18

    申请人： Ryuji Kohno ,  Hideo Miura ,  Yoshishige Endo ,  Masatoshi Kanamaru ,  Atsushi Hosogane ,  Hideyuki Aoki ,  Naoto Ban

    发明人： Ryuji Kohno ,  Hideo Miura ,  Yoshishige Endo ,  Masatoshi Kanamaru ,  Atsushi Hosogane ,  Hideyuki Aoki ,  Naoto Ban

    IPC分类号： G01R3102

    CPC分类号： H01L22/32 ,  G01R1/06711 ,  G01R1/06738 ,  G01R1/07314 ,  G01R3/00 ,  H01L23/13 ,  H01L2924/0002 ,  H01L2924/13091 ,  H01L2924/00

    摘要： A semiconductor inspection apparatus which is possible to inspect a plurality of semiconductor devices collectively at one time, which has conventionally been difficult because of precision or the like of probes. A method of manufacturing the semiconductor inspection apparatus comprises the steps of forming a cover film on a surface of the silicon substrate and forming a plurality of probes of a polygonal cone shape or a circular cone shape through etching after patterning by photolithography, after the cover film is removed, again forming a cover film on the surface of the silicon substrate and forming a beam or a diaphragm for each probe through etching after patterning by photolithography, after the cover film is removed, again forming a cover film on the surface of the silicon substrate and forming a through hole corresponding to the probe through etching after patterning by photolithography, and after the cover film is removed, forming an insulating film on the surface of the silicon substrate, forming a metal film on a surface of the insulating film, and forming a wiring lead through etching after patterning by photolithography.

    摘要翻译： 可以一次共同地检查多个半导体器件的半导体检查装置，由于探针的精度等，以前难以进行。 一种制造半导体检查装置的方法包括以下步骤：在硅衬底的表面上形成覆盖膜，并通过光刻图案化之后通过蚀刻形成多个锥形或圆锥形的多个探针， 被去除，再次在硅衬底的表面上形成覆盖膜，并且通过光刻在图案化之后通过蚀刻形成用于每个探针的光束或隔膜，在除去覆盖膜之后，再次在硅表面上形成覆盖膜 在通过光刻图案化之后通过蚀刻形成与探针对应的通孔，并且在除去覆盖膜之后，在硅衬底的表面上形成绝缘膜，在绝缘膜的表面上形成金属膜，以及 通过光刻在图案化之后通过蚀刻形成布线引线。

    Method for manufacturing substrate for inspecting semiconductor device
    8.
    发明授权
    Method for manufacturing substrate for inspecting semiconductor device 失效
    用于检查半导体器件的衬底的制造方法

    公开(公告)号：US06566149B1

    公开(公告)日：2003-05-20

    申请号：US09787250

    申请日：2001-03-16

    申请人： Masatoshi Kanamaru ,  Atsushi Hosogane ,  Yoshihige Endou ,  Ryuji Kouno ,  Hideo Miura ,  Shinji Tanaka ,  Hiroyuki Ohta ,  Akihiko Ariga ,  Naoto Ban ,  Hideyuki Aoki

    发明人： Masatoshi Kanamaru ,  Atsushi Hosogane ,  Yoshihige Endou ,  Ryuji Kouno ,  Hideo Miura ,  Shinji Tanaka ,  Hiroyuki Ohta ,  Akihiko Ariga ,  Naoto Ban ,  Hideyuki Aoki

    IPC分类号： G01R3126

    CPC分类号： G01R3/00

    摘要： For an inspection tray, a silicon substrate including a beam or a diaphragm, a probe and wiring is used. To highly accurately position a chip to be inspected, a second substrate for alignment is disposed on the substrate. To position the probe having wiring disposed on the first substrate and the electrode pad of the chip to be inspected, a projection or a groove is formed in each of both substrates. Preferably, the projection or groove should be formed by silicon anisotorpic etching to have a (111) crystal surface. As another machining method, dry etching can be used for machining the positioning projection or groove. By using an inductively coupled plasma-reactive ion etching (ICP-RIE) device for the dry etching, a vertical column or groove can be easily machined.

    摘要翻译： 对于检查托盘，使用包括梁或隔膜，探针和布线的硅基板。 为了高精度地定位待检查的芯片，在基板上设置用于对准的第二基板。 为了定位具有设置在第一基板上的布线的探针和要检查的芯片的电极焊盘，在两个基板中的每一个中形成突起或凹槽。 优选地，突起或凹槽应由硅各向异性蚀刻形成以具有（111）晶体表面。 作为另一种加工方法，可以使用干蚀刻来加工定位突起或凹槽。 通过使用用于干蚀刻的电感耦合等离子体反应离子蚀刻（ICP-RIE）装置，可以容易地加工垂直的柱或槽。

    Semiconductor device testing apparatus and method for manufacturing the same
    10.
    发明授权
    Semiconductor device testing apparatus and method for manufacturing the same 失效
    半导体器件测试装置及其制造方法

    公开(公告)号：US06828810B2

    公开(公告)日：2004-12-07

    申请号：US10207145

    申请日：2002-07-30

    申请人： Masatoshi Kanamaru ,  Yoshishige Endo ,  Takanori Aono ,  Ryuji Kohno ,  Hiroya Shimizu ,  Naoto Ban ,  Hideyuki Aoki

    发明人： Masatoshi Kanamaru ,  Yoshishige Endo ,  Takanori Aono ,  Ryuji Kohno ,  Hiroya Shimizu ,  Naoto Ban ,  Hideyuki Aoki

    IPC分类号： G01R3102

    CPC分类号： G01R1/0466

    摘要： A semiconductor device testing apparatus is realized, which allows contactors to be positioned throughout the wafer surface highly accurately for uniform contact, testing a large-sized wafer, and cost reduction. A plurality of divided contactor blocks is formed with a positioning groove. The groove is used to position the plurality of contactor blocks with a positioning frame. Because the contactor blocks are divided into plurals, it is less likely that a partial surface distortion affects other portions to impair surface flatness as compared with the case where a plurality of non-divided contactors is formed integrally, and the plurality of contactor blocks can be brought into contact with a wafer to be tested uniformly. Additionally, even though abnormality is generated in a part of the contactor blocks, only the part of the contactor blocks is replaced. Therefore, replacement costs can be reduced as compared with the case where a plurality of non-divided contactors is formed integrally.

    摘要翻译： 实现半导体器件测试装置，其允许接触器高精度地定位在整个晶片表面，用于均匀接触，测试大尺寸晶片以及降低成本。 多个分开的接触器块形成有定位槽。 凹槽用于定位具有定位框架的多个接触器块。 由于接触器块被分成多个，与多个非分隔接触器形成为一体的情况相比，部分表面变形对其他部分的影响较小可能损害表面平坦度，并且多个接触器块可以 与待测试的晶片均匀接触。 此外，即使在接触器块的一部分中产生异常，仅更换接触器块的一部分。 因此，与多个非分割接触器一体形成的情况相比，可以降低更换成本。