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公开(公告)号：US06330684B1
公开(公告)日：2001-12-11
申请号：US09147663
申请日：1999-02-09
IPC分类号： G06F1100
CPC分类号： H03M13/6502 , H03M13/3961 , H03M13/4107 , H03M13/4169 , H03M13/6561 , H03M13/6563 , H03M13/6569
摘要： Two path metrics (PM0, PM1) are read from path metric storing means 1, and two path metrics (BM0, BM1) are read from branch metric storing means 3. An ACS operation is executed using PM0+MB0 and PM1+BM1 by comparing means 5, adding means 6, comparison result storing means 7, and selecting means 8. In parallel with the ACS operation, an ACS operation is executed using PM0+MB1 and PM1+BM0 by comparing means 9, adding means 10, comparison result storing means 11, and selecting means 12.
摘要翻译： 从路径量度存储装置1读取两个路径度量（PM0，PM1），并从分支度量存储装置3读取两个路径度量（BM0，BM1）。通过比较使用PM0 + MB0和PM1 + BM1执行ACS操作 装置5，加法装置6，比较结果存储装置7和选择装置8.与ACS操作并行地，通过比较装置9，加法装置10，使用PM0 + MB1和PM1 + BM0执行ACS操作，比较结果存储 装置11和选择装置12。
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公开(公告)号：US06477661B2
公开(公告)日：2002-11-05
申请号：US09974807
申请日：2001-10-12
IPC分类号： G06F1100
CPC分类号： H03M13/6502 , H03M13/3961 , H03M13/4107 , H03M13/4169 , H03M13/6561 , H03M13/6563 , H03M13/6569
摘要： A method of operating a digital signal processor is provided. The digital signal processor may be provided as a radio communication mobile station, a radio communication base station apparatus, or a CDMA radio communication system. Each path metric PM1 and PM0 of an old state is added to each branch metric BM1 and BM0 separately. A path metric of a new state N is formed by comparing the value of PM1+BM1 to the value of PM0+BM0. A path metric of a new state N+2k−2 is formed by comparing the value of PM1+BM0 to PM0+BM1.
摘要翻译： 提供了一种操作数字信号处理器的方法。 数字信号处理器可以被提供为无线电通信移动台，无线电通信基站装置或CDMA无线电通信系统。 将旧状态的每个路径度量PM1和PM0分别添加到每个分支量度BM1和BM0。 通过将PM1 + BM1的值与PM0 + BM0的值进行比较来形成新状态N的路径度量。 通过将PM1 + BM0的值与PM0 + BM1进行比较来形成新状态N + 2k-2的路径度量。
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3.发明授权公开(公告)号：US07325184B2
公开(公告)日：2008-01-29
申请号：US11022811
申请日：2004-12-28
IPC分类号： H03M13/03
CPC分类号： H03M13/6502 , H03M13/3961 , H03M13/4107 , H03M13/4169 , H03M13/6561 , H03M13/6563 , H03M13/6569
摘要： A digital signal processor includes a functional unit configured to execute instructions. The functional unit determines a first minimum data of a first data and a second data, in parallel with a determination of a second minimum data of a third data and a fourth data. The functional unit outputs processed data including the first minimum data and the second minimum data. Each bit length of the first minimum data and the second minimum data is equal to n bits in length. A bit length of the processed data is equal to 2 n bits in length.
摘要翻译： 数字信号处理器包括被配置为执行指令的功能单元。 功能单元与第三数据和第四数据的第二最小数据的确定并行地确定第一数据和第二数据的第一最小数据。 功能单元输出包括第一最小数据和第二最小数据的处理数据。 第一最小数据和第二最小数据的每个位长度等于n位长度。 处理后的数据的位长度等于2 n位长。
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公开(公告)号：US07139968B2
公开(公告)日：2006-11-21
申请号：US10748242
申请日：2003-12-31
IPC分类号： H03M13/03
CPC分类号： H03M13/6502 , H03M13/3961 , H03M13/4107 , H03M13/4169 , H03M13/6561 , H03M13/6563 , H03M13/6569
摘要： A digital signal processor configured to perform a Viterbi algorithm includes an instruction fetching unit that fetches instructions and a decoding unit that decodes the instructions fetched by the instruction fetching unit. The digital signal processor also includes an execution unit that executes the instructions decoded by the decoding unit. The execution unit includes an arithmetic logic unit configured to perform a register—register arithmetic logic operation. The arithmetic logic unit compares a first data with a second data, in parallel with a comparison of a third data with a fourth data, and the execution unit outputs new path metrics. Each of the first data, the second data, the third data, and the fourth data is one of four results obtained by adding one of two path metrics to one of two branch metrics.
摘要翻译： 被配置为执行维特比算法的数字信号处理器包括取指令的指令取出单元和对由指令取出单元取出的指令进行解码的解码单元。 数字信号处理器还包括执行由解码单元解码的指令的执行单元。 执行单元包括被配置为执行寄存器寄存器算术逻辑运算的算术逻辑单元。 算术逻辑单元与第三数据与第四数据的比较并行地将第一数据与第二数据进行比较，并且执行单元输出新的路径度量。 第一数据，第二数据，第三数据和第四数据中的每一个是通过将两个路径度量中的一个添加到两个分支度量之一而获得的四个结果之一。
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公开(公告)号：US20050163233A1
公开(公告)日：2005-07-28
申请号：US11022811
申请日：2004-12-28
CPC分类号： H03M13/6502 , H03M13/3961 , H03M13/4107 , H03M13/4169 , H03M13/6561 , H03M13/6563 , H03M13/6569
摘要： A digital signal processor includes a functional unit configured to execute instructions. The functional unit determines a first minimum data of a first data and a second data, in parallel with a determination of a second minimum data of a third data and a fourth data. The functional unit outputs processed data including the first minimum data and the second minimum data. Each bit length of the first minimum data and the second minimum data is equal to n bits in length. A bit length of the processed data is equal to 2n bits in length.
摘要翻译： 数字信号处理器包括被配置为执行指令的功能单元。 功能单元与第三数据和第四数据的第二最小数据的确定并行地确定第一数据和第二数据的第一最小数据。 功能单元输出包括第一最小数据和第二最小数据的处理数据。 第一最小数据和第二最小数据的每个位长度等于n位长度。 处理数据的位长度等于2n位长。
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公开(公告)号：US06735714B2
公开(公告)日：2004-05-11
申请号：US10252394
申请日：2002-09-24
IPC分类号： G06F1100
CPC分类号： H03M13/6502 , H03M13/3961 , H03M13/4107 , H03M13/4169 , H03M13/6561 , H03M13/6563 , H03M13/6569
摘要： A digital signal processor capable of performing a Viterbi algorithm is provided. The digital signal processor includes an instruction fetching unit that fetches instructions; a decoding unit that decodes the instructions fetched by the instruction fetching unit, and an execution unit that executes the instructions decoded by the decoding unit. The execution unit includes a first comparing unit that compares first data with second data and a second comparing unit that compares third data with fourth data. The first comparing unit and the second comparing unit operate in parallel. Also, the first data, the second data, the third data, and the fourth data can each be one of four results obtained by adding one of two path metrics to one of two branch metrics. The execution unit outputs any two new path metrics in a high order position and a low order position respectively.
摘要翻译： 提供能够执行维特比算法的数字信号处理器。 数字信号处理器包括取指令的指令取出单元; 对由指令取出单元取出的指令进行解码的解码单元，以及执行由解码单元解码的指令的执行单元。 执行单元包括将第一数据与第二数据进行比较的第一比较单元和将第三数据与第四数据进行比较的第二比较单元。 第一比较单元和第二比较单元并行操作。 此外，第一数据，第二数据，第三数据和第四数据可以分别是通过将两个路径度量中的一个添加到两个分支度量之一而获得的四个结果之一。 执行单元分别在高阶位置和低位置输出任何两个新的路径度量。
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公开(公告)号：US08723777B2
公开(公告)日：2014-05-13
申请号：US13560682
申请日：2012-07-27
CPC分类号： G09G3/2096 , G09G3/2003 , G09G3/3611 , G09G2340/02 , G09G2340/145
摘要： A panel control device includes a programmable array. This programmable array operates in accordance with a configuration code and includes a plurality of first-class elements and at least one second-class element. This provides a panel control device requiring a small circuit area, being suitable for system-on-chip (SoC) mounting, and driving a liquid crystal display device having various specifications also in the future.
摘要翻译： 面板控制装置包括可编程阵列。 该可编程阵列根据配置代码进行操作并且包括多个第一类元素和至少一个第二类元素。 这提供了一种面板控制装置，其需要小的电路面积，适用于系统级芯片（SoC）安装，并且在将来也驱动具有各种规格的液晶显示装置。
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公开(公告)号：US06363469B1
公开(公告)日：2002-03-26
申请号：US09351733
申请日：1999-07-12
申请人： Minoru Okamoto , Hidetoshi Suzuki
发明人： Minoru Okamoto , Hidetoshi Suzuki
IPC分类号： G06F934
CPC分类号： G06F9/355 , G06F9/30101 , G06F9/345
摘要： An address generation apparatus for generating a first address and a second address includes a first register for storing a first reference address; a second register for storing a second reference address; a third register for storing a first offset value with respect to the first reference address, the first offset value being designated by an instruction; a fourth register for storing a second offset value with respect to the second reference address, the second offset value being designated by the instruction; a first adder for adding the first reference address stored in the first register and the first offset value stored in the third register; a second adder for adding the second reference address stored in the second register and the second offset value stored in the fourth register; a fifth register for storing an output from the first adder as the first address; and a sixth register for storing an output from the second adder as the second address.
摘要翻译： 一种用于产生第一地址和第二地址的地址产生装置包括用于存储第一参考地址的第一寄存器; 用于存储第二参考地址的第二寄存器; 第三寄存器，用于存储关于第一参考地址的第一偏移值，第一偏移值由指令指定; 第四寄存器，用于存储关于第二参考地址的第二偏移值，第二偏移值由指令指定; 第一加法器，用于将存储在第一寄存器中的第一参考地址和存储在第三寄存器中的第一偏移值相加; 第二加法器，用于将存储在第二寄存器中的第二参考地址和存储在第四寄存器中的第二偏移值相加; 第五寄存器，用于存储来自第一加法器的输出作为第一地址; 以及第六寄存器，用于存储来自第二加法器的输出作为第二地址。
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公开(公告)号：US06751773B2
公开(公告)日：2004-06-15
申请号：US09833061
申请日：2001-04-12
IPC分类号： H03M1303
CPC分类号： H03M13/23
摘要： A coding apparatus includes shift register, input register and logical operation section. The shift register performs bit shifting on an input bit sequence and stores one bit of the input bit sequence after another. The input register stores coefficients of terms on respective orders of a generator polynomial. The logical operation section obtains logical products of the respective bits stored on the shift register and associated bits stored on the input register and a logical product of each one bit input to the shift register and an associated bit stored on the input register so that the earlier a bit of the input bit sequence was input, the higher-order one of the coefficients in the terms of the polynomial the input bit is associated with. Next, the logical operation section derives an exclusive logical sum of the products and then outputs the sum as a bit of a code sequence.
摘要翻译： 编码装置包括移位寄存器，输入寄存器和逻辑运算部。 移位寄存器在输入位序列上执行位移位，并将输入位序列的一位相继存储。 输入寄存器存储关于生成多项式的各个阶的项的系数。 逻辑运算部分获得存储在移位寄存器上的相应位的逻辑积和存储在输入寄存器上的相关位以及输入到移位寄存器的每一位的逻辑积和存储在输入寄存器上的关联位， 输入一位输入比特序列，输入比特关联的多项式项中的系数中的高阶一个。 接下来，逻辑运算部分导出乘积的异或逻辑和，然后输出和作为代码序列的位。
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公开(公告)号：US06289429B1
公开(公告)日：2001-09-11
申请号：US08812711
申请日：1997-03-06
申请人： Minoru Okamoto
发明人： Minoru Okamoto
IPC分类号： G06F1200
摘要： A memory device including a first memory and a second memory. A first processor generates a first address for defining a location to be accessed in the first memory and a second address for defining a location to be accessed in the second memory. A second processor generates a third address. A memory control section controls access to the first memory and access to the second memory. The memory control section includes an address conversion section for converting the third address so as to represent either one of the first address and the second address.
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