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公开(公告)号：US20240063262A1
公开(公告)日：2024-02-22
申请号：US18127298
申请日：2023-03-28
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Yong Uk Jeon , Kyung Ho Kim , Ki Hwan Kim , Kang Hun Moon , Cho Eun Lee
IPC: H01L29/06 , H01L29/66 , H01L29/775 , H01L29/423 , H01L29/786 , H01L27/092
CPC classification number: H01L29/0673 , H01L29/66545 , H01L29/775 , H01L29/42392 , H01L29/78696 , H01L29/66553 , H01L27/092
Abstract: A semiconductor device is provided. The semiconductor device includes: an active pattern extending in on a substrate; nanosheets stacked on the active pattern; a gate electrode on the active pattern and surrounding the nanosheets; a source/drain trench on the active pattern adjacent the gate electrode; and a source/drain region in the source/drain trench, The source/drain region includes: a first layer provided along a sidewall and a bottom surface of the source/drain trench, the first layer having a first n-type impurity doped therein; a second layer on the first layer in the source/drain trench, the second layer having germanium (Ge) doped therein; and a third layer filling a remaining portion of the source/drain trench on the second layer, the third layer having a second n-type impurity doped therein.
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公开(公告)号：US10084049B2
公开(公告)日：2018-09-25
申请号：US15685255
申请日：2017-08-24
Applicant: Samsung Electronics Co., Ltd.
Inventor： Jin Bum Kim , Gyeom Kim , Seok Hoon Kim , Tae Jin Park , Jeong Ho Yoo , Cho Eun Lee , Hyun Jung Lee , Sun Jung Kim , Dong Suk Shin
IPC: H01L27/12 , H01L29/417 , H01L27/092 , H01L29/51 , H01L29/423 , H01L21/02 , H01L21/3205
CPC classification number: H01L29/41725 , H01L21/02425 , H01L21/28518 , H01L21/32053 , H01L21/823814 , H01L21/823821 , H01L23/485 , H01L27/0924 , H01L29/0847 , H01L29/165 , H01L29/41791 , H01L29/42356 , H01L29/517 , H01L29/66545 , H01L29/7848 , H01L2924/0002
Abstract: A semiconductor device includes: a substrate having an active region; a gate structure disposed in the active region; source/drain regions respectively formed within portions of the active region disposed on both sides of the gate structure; a metal silicide layer disposed on a surface of each of the source/drain regions; and contact plugs disposed on the source/drain regions and electrically connected to the source/drain regions through the metal silicide layer, respectively. The metal silicide layer is formed so as to have a monocrystalline structure.
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公开(公告)号：US11728434B2
公开(公告)日：2023-08-15
申请号：US17011221
申请日：2020-09-03
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Seok Hoon Kim , Dong Myoung Kim , Dong Suk Shin , Seung Hun Lee , Cho Eun Lee , Hyun Jung Lee , Sung Uk Jang , Edward Nam Kyu Cho , Min-Hee Choi
IPC: H01L29/78 , H01L29/66 , H01L21/8234 , H01L21/768 , H01L21/02 , H01L29/423 , H01L29/165 , H01L27/088 , H01L29/08 , H01L29/49 , H01L27/12
CPC classification number: H01L29/7855 , H01L21/02532 , H01L21/76871 , H01L21/823431 , H01L27/0886 , H01L29/0847 , H01L29/165 , H01L29/4232 , H01L29/6656 , H01L29/66795 , H01L29/785 , H01L21/02645 , H01L27/1211 , H01L29/4966 , H01L29/66545
Abstract: A semiconductor device includes a first fin type pattern on a substrate, a second fin type pattern, parallel to the first fin type pattern, on the substrate, and an epitaxial pattern on the first and second fin type patterns. The epitaxial pattern may include a shared semiconductor pattern on the first fin type pattern and the second fin type pattern. The shared semiconductor pattern may include a first sidewall adjacent to the first fin type pattern and a second sidewall adjacent to the second fin type pattern. The first sidewall may include a first lower facet, a first upper facet on the first lower facet and a first connecting curved surface connecting the first lower and upper facets. The second sidewall may include a second lower facet, a second upper facet on the second lower facet and a second connecting curved surface connecting the second lower and upper facets.
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公开(公告)号：US10128112B2
公开(公告)日：2018-11-13
申请号：US15595945
申请日：2017-05-16
Applicant: Samsung Electronics Co., Ltd.
Inventor： Cho Eun Lee , Jin Bum Kim , Kang Hun Moon , Jae Myung Choe , Sun Jung Kim , Dong Suk Shin , Il Gyou Shin , Jeong Ho Yoo
IPC: H01L21/336 , H01L21/02 , H01L21/223 , H01L29/66
Abstract: A method of fabricating a semiconductor device is provided. The method includes forming a dummy gate electrode on a substrate, forming a trench on a side surface of the dummy gate electrode, performing a bake process of removing an impurity from the trench and forming a source/drain in the trench, wherein the bake process comprises a first stage and a second stage following the first stage, an air pressure in which the substrate is disposed during the first stage is different from an air pressure in which the substrate is disposed during the second stage, and the bake process is performed while the substrate is on a stage rotating the substrate, wherein a revolution per minute (RPM) of the substrate during the first stage is different from a revolution per minute (RPM) of the substrate during the second stage.
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公开(公告)号：US10008600B2
公开(公告)日：2018-06-26
申请号：US15685459
申请日：2017-08-24
Applicant: Samsung Electronics Co., Ltd.
Inventor： Nam Kyu Kim , Dong Chan Suh , Kwan Heum Lee , Byeong Chan Lee , Cho Eun Lee , Su Jin Jung , Gyeom Kim , Ji Eon Yoon
IPC: H01L29/08 , H01L29/78 , H01L29/165 , H01L29/417
CPC classification number: H01L29/7848 , H01L29/0847 , H01L29/165 , H01L29/41766 , H01L29/7834
Abstract: A semiconductor device may include: a semiconductor substrate, a device isolating layer embedded within the semiconductor substrate and defining an active region, a channel region formed in the active region, a gate electrode disposed above the channel region, a gate insulating layer provided between the channel region and the gate electrode, and a silicon germanium epitaxial layer adjacent to the channel region within the active region and including a first epitaxial layer containing a first concentration of germanium, a second epitaxial layer containing a second concentration of germanium, higher than the first concentration, and a third epitaxial layer containing a third concentration of germanium, lower than the second concentration, the first to third epitaxial layers being sequentially stacked on one another in that order.
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公开(公告)号：US10784379B2
公开(公告)日：2020-09-22
申请号：US15995414
申请日：2018-06-01
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Seok Hoon Kim , Dong Myoung Kim , Dong Suk Shin , Seung Hun Lee , Cho Eun Lee , Hyun Jung Lee , Sung Uk Jang , Edward Nam Kyu Cho , Min-Hee Choi
IPC: H01L29/78 , H01L29/66 , H01L21/8234 , H01L21/768 , H01L21/02 , H01L29/423 , H01L29/165 , H01L27/088 , H01L29/08 , H01L29/49 , H01L27/12
Abstract: A semiconductor device includes a first fin type pattern on a substrate, a second fin type pattern, parallel to the first fin type pattern, on the substrate, and an epitaxial pattern on the first and second fin type patterns. The epitaxial pattern may include a shared semiconductor pattern on the first fin type pattern and the second fin type pattern. The shared semiconductor pattern may include a first sidewall adjacent to the first fin type pattern and a second sidewall adjacent to the second fin type pattern. The first sidewall may include a first lower facet, a first upper facet on the first lower facet and a first connecting curved surface connecting the first lower and upper facets. The second sidewall may include a second lower facet, a second upper facet on the second lower facet and a second connecting curved surface connecting the second lower and upper facets.
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公开(公告)号：US09761719B2
公开(公告)日：2017-09-12
申请号：US14741454
申请日：2015-06-17
Applicant: Samsung Electronics Co., Ltd.
Inventor： Nam Kyu Kim , Dong Chan Suh , Kwan Heum Lee , Byeong Chan Lee , Cho Eun Lee , Su Jin Jung , Gyeom Kim , Ji Eon Yoon
IPC: H01L27/088 , H01L29/78 , H01L29/417 , H01L29/08 , H01L29/165
CPC classification number: H01L29/7848 , H01L29/0847 , H01L29/165 , H01L29/41766 , H01L29/7834
Abstract: A semiconductor device may include: a semiconductor substrate, a device isolating layer embedded within the semiconductor substrate and defining an active region, a channel region formed in the active region, a gate electrode disposed above the channel region, a gate insulating layer provided between the channel region and the gate electrode, and a silicon germanium epitaxial layer adjacent to the channel region within the active region and including a first epitaxial layer containing a first concentration of germanium, a second epitaxial layer containing a second concentration of germanium, higher than the first concentration, and a third epitaxial layer containing a third concentration of germanium, lower than the second concentration, the first to third epitaxial layers being sequentially stacked on one another in that order.
