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公开(公告)号：US20240221834A1
公开(公告)日：2024-07-04
申请号：US18357407
申请日：2023-07-24
Applicant: Samsung Electronics Co., Ltd.
Inventor： Hoseok HEO , Hyungyung KIM , Seungdam HYUN , Kyunghun KIM , Seungyeul YANG , Gukhyon YON , Minhyun LEE , Seokhoon CHOI
CPC classification number: G11C16/0483 , H10B43/27
Abstract: A vertical non-volatile memory device and an electronic apparatus including the vertical non-volatile memory device are provided. The vertical non-volatile memory device includes a pillar, a channel layer surrounding a side surface of the pillar, a charge tunneling layer surrounding a side surface of the channel layer, a charge trap layer surrounding a side surface of the charge tunneling layer and including an amorphous oxynitride, a charge blocking layer surrounding a side surface of the charge trap layer, and a plurality of separation layers and a plurality of gate electrodes surrounding a side surface of the charge blocking layer and alternately arranged along the side surface of the charge blocking layer.
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公开(公告)号：US20240224530A1
公开(公告)日：2024-07-04
申请号：US18215533
申请日：2023-06-28
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Seungdam HYUN , Kyunghun KIM , Sunho KIM , Hyungyung KIM , Kwangmin PARK , Seungyeul YANG , Gukhyon YON , Minhyun LEE , Seokhoon CHOI , Hoseok HEO
IPC: H10B43/35 , G11C16/04 , H01L29/423 , H10B43/10 , H10B43/27
CPC classification number: H10B43/35 , G11C16/0483 , H01L29/4234 , H10B43/10 , H10B43/27
Abstract: A vertical NAND flash memory device includes a plurality of cell arrays, where each cell array of the plurality of cell arrays includes a channel layer, a charge trap layer provided on the channel layer, the charge trap layer including a matrix comprising a dielectric and a charge trap material in the matrix and including anti-ferroelectric nanocrystals or ferroelectric nanocrystals, and a plurality of gate electrodes provided on the charge trap layer.
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公开(公告)号：US20240215249A1
公开(公告)日：2024-06-27
申请号：US18322365
申请日：2023-05-23
Applicant: Samsung Electronics Co., Ltd.
Inventor： Kyunghun KIM , Sunho KIM , Seyun KIM , Hyungyung KIM , Seungyeul YANG , Gukhyon YON , Minhyun LEE , Seokhoon CHOI , Hoseok HEO
Abstract: A vertical NAND flash memory device may include a plurality of cell arrays. Each of the plurality of cell arrays may include a channel layer, a charge trap layer on the channel layer, and a plurality of gate electrodes on the charge trap layer. The charge trap layer may include silicon oxynitride comprising a metal. The metal may include at least one of Ga or In.
