公开(公告)号：US09514813B2

公开(公告)日：2016-12-06

申请号：US14724909

申请日：2015-05-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yong-kyu Lee ,  Yeong-taek Lee ,  Dae-seok Byeon ,  In-gyu Baek ,  Man Chang ,  Lijie Zhang

IPC: G11C11/00 ,  G11C13/00 ,  G11C7/04 ,  G11C11/16

CPC classification number: G11C13/0069 ,  G11C7/04 ,  G11C11/1659 ,  G11C11/1675 ,  G11C13/0097 ,  G11C2013/0073 ,  G11C2013/0088 ,  G11C2013/0092

Abstract: A method for operating a memory device includes sensing a temperature of the resistive memory device, setting a level of a set voltage or current for writing to a memory cell based on the temperature, setting a level of a reset voltage for reset writing to the memory cell based on the temperature, and performing a write operation on the memory cell based on the level of the set voltage or current and the level of the reset voltage. The memory device may be a resistive memory device.

Abstract translation: 一种用于操作存储器件的方法包括：感测电阻性存储器件的温度，根据温度设置用于写入存储器单元的设定电压或电流的电平，设置用于复位写入的复位电压的电平到存储器 基于温度，并且基于设定电压或电流的电平以及复位电压的电平对存储器单元执行写入操作。 存储器件可以是电阻式存储器件。

公开(公告)号：US08730710B2

公开(公告)日：2014-05-20

申请号：US14017856

申请日：2013-09-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： In-gyu Baek ,  Hong-sun Hwang ,  Hak-soo Yu ,  Chul-woo Park

IPC: G11C11/00

CPC classification number: H01L45/147 ,  G11C5/025 ,  G11C13/0002 ,  G11C2213/71 ,  G11C2213/72 ,  H01L27/2409 ,  H01L27/2481 ,  H01L45/14

Abstract: Semiconductor memory device having a stacking structure including resistor switch based logic circuits. The semiconductor memory device includes a first conductive line that includes a first line portion and a second line portion, wherein the first line portion and the second line portion are electrically separated from each other by an intermediate region disposed between the first and second line portions, a first variable resistance material film that is connected to the first line portion and stores data, and a second variable resistance material film that controls an electrical connection between the first line portion and the second line portion.

Abstract translation: 具有包括基于电阻器开关的逻辑电路的堆叠结构的半导体存储器件。 半导体存储器件包括第一导线，其包括第一线部分和第二线部分，其中第一线部分和第二线部分通过布置在第一线部分和第二线部分之间的中间区域彼此电分离， 连接到第一线部分并存储数据的第一可变电阻材料膜和控制第一线部分和第二线部分之间的电连接的第二可变电阻材料膜。

公开(公告)号：US11508775B2

公开(公告)日：2022-11-22

申请号：US17398493

申请日：2021-08-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Gang Zhang ,  Shi Li Quan ,  Hyung-yong Kim ,  Seug-gab Park ,  In-gyu Baek ,  Kyung-rae Byun ,  Jin-yong Choi

IPC: H01L27/146 ,  H04N5/335

Abstract: The inventive concepts provide a three-dimensional (3D) image sensor, based on structured light (SL), having a structure in which difficulty in a manufacturing process of a wiring layer is decreased and/or an area of a bottom pad of a capacitor is increased. The 3D image sensor includes: a pixel area including a photodiode in a semiconductor substrate and a gate group including a plurality of gates; a multiple wiring layer on an upper portion of the pixel area, the multiple wiring layer including at least two wiring layers; and a capacitor structure between a first wiring layer on a lowermost wiring layer of the multiple wiring layer and a second wiring layer on the first wiring layer, the capacitor structure including a bottom pad, a top pad, and a plurality of capacitors, wherein the bottom pad is connected to the first wiring layer.

公开(公告)号：US20140008598A1

公开(公告)日：2014-01-09

申请号：US14017856

申请日：2013-09-04

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： In-gyu Baek ,  Hong-sun Hwang ,  Hak-soo Yu ,  Chul-woo Park

IPC: H01L45/00

CPC classification number: H01L45/147 ,  G11C5/025 ,  G11C13/0002 ,  G11C2213/71 ,  G11C2213/72 ,  H01L27/2409 ,  H01L27/2481 ,  H01L45/14

Abstract: Semiconductor memory device having a stacking structure including resistor switch based logic circuits. The semiconductor memory device includes a first conductive line that includes a first line portion and a second line portion, wherein the first line portion and the second line portion are electrically separated from each other by an intermediate region disposed between the first and second line portions, a first variable resistance material film that is connected to the first line portion and stores data, and a second variable resistance material film that controls an electrical connection between the first line portion and the second line portion.

Abstract translation: 具有包括基于电阻器开关的逻辑电路的堆叠结构的半导体存储器件。 半导体存储器件包括第一导线，其包括第一线部分和第二线部分，其中第一线部分和第二线部分通过布置在第一线部分和第二线部分之间的中间区域彼此电分离， 连接到第一线部分并存储数据的第一可变电阻材料膜和控制第一线部分和第二线部分之间的电连接的第二可变电阻材料膜。

公开(公告)号：US11183527B2

公开(公告)日：2021-11-23

申请号：US16410386

申请日：2019-05-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Gang Zhang ,  Shi Li Quan ,  Hyung-yong Kim ,  Seug-gab Park ,  In-gyu Baek ,  Kyung-rae Byun ,  Jin-yong Choi

IPC: H01L27/146 ,  H04N5/335

Abstract: The inventive concepts provide a three-dimensional (3D) image sensor, based on structured light (SL), having a structure in which difficulty in a manufacturing process of a wiring layer is decreased and/or an area of a bottom pad of a capacitor is increased. The 3D image sensor includes: a pixel area including a photodiode in a semiconductor substrate and a gate group including a plurality of gates; a multiple wiring layer on an upper portion of the pixel area, the multiple wiring layer including at least two wiring layers; and a capacitor structure between a first wiring layer on a lowermost wiring layer of the multiple wiring layer and a second wiring layer on the first wiring layer, the capacitor structure including a bottom pad, a top pad, and a plurality of capacitors, wherein the bottom pad is connected to the first wiring layer.

公开(公告)号：US09728252B2

公开(公告)日：2017-08-08

申请号：US14796131

申请日：2015-07-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yong-kyu Lee ,  Yeong-taek Lee ,  Dae-seok Byeon ,  In-gyu Baek ,  Man Chang ,  Lijie Zhang ,  Hyun-kook Park

IPC: G11C7/04 ,  G11C13/00 ,  G11C11/56 ,  G11C11/16

CPC classification number: G11C13/004 ,  G11C7/04 ,  G11C11/1673 ,  G11C11/5607 ,  G11C11/5678 ,  G11C11/5685 ,  G11C13/0004 ,  G11C13/0064 ,  G11C2013/0054

Abstract: A method for operating a memory device includes sensing a change in temperature of the memory device, adjusting a level of a reference current for a read operation, and reading data from memory cells of the memory device based on the adjusted level of the reference current. The level of the reference current is adjusted from a reference value to a first value when the temperature of the memory device increases and is adjusted from the reference value to a second value when the temperature of the memory device decreases. A difference between the reference value and the first value is different from a difference the reference value and the second value.

公开(公告)号：US09633727B2

公开(公告)日：2017-04-25

申请号：US14830377

申请日：2015-08-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Man Chang ,  In-gyu Baek ,  Sang-heon Lee ,  Hyun-sang Hwang

IPC: G11C11/00 ,  G11C13/00 ,  G11C11/56

CPC classification number: G11C13/0069 ,  G11C11/5678 ,  G11C11/5685 ,  G11C13/0064 ,  G11C2013/0092

Abstract: A method of controlling a resistive memory device includes: accessing a first pulse power specification satisfying a memory cell coefficient associated with at least a first of a plurality of memory cells included in a memory cell array; generating a first pulse power according to the accessed first pulse power specification; and performing a write operation on at least the first of the plurality of memory cells using the generated first pulse power.