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公开(公告)号：US09786600B2
公开(公告)日：2017-10-10
申请号：US14970160
申请日：2015-12-15
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Sung-Il Cho , Nam-Gun Kim , Jin-Young Kim , Hyun-Chul Yoon , Bong-Soo Kim , Kwan-Sik Cho
IPC: H01L27/00 , H01L29/00 , H01L23/00 , H01L23/528 , H01L29/423 , H01L29/78 , H01L27/105 , H01L29/45 , H01L23/535 , H01L29/06 , H01L27/108
CPC classification number: H01L23/528 , H01L23/535 , H01L27/1052 , H01L27/10873 , H01L27/10876 , H01L27/10885 , H01L27/10888 , H01L27/10894 , H01L27/10897 , H01L29/0649 , H01L29/42324 , H01L29/45 , H01L29/78 , H01L29/7827 , H01L2924/0002 , H01L2924/00
Abstract: A semiconductor device having a cell area and a peripheral area includes a semiconductor substrate, a cell insulating isolation region delimiting a cell active region of the semiconductor substrate in the cell area, a word line disposed within the semiconductor substrate in the cell area, a bit line contact plug disposed on the cell active region, a bit line disposed on the bit line contact plug, a peripheral insulating isolation region delimiting a peripheral active region of the semiconductor substrate in the peripheral area, and a peripheral transistor including a peripheral transistor lower electrode and a peripheral transistor upper electrode. The bit line contact plug is formed at the same level in the semiconductor device as the peripheral transistor lower electrode, and the bit line electrode is formed at the same level in the semiconductor device as the peripheral transistor upper electrode.
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公开(公告)号：US10553449B2
公开(公告)日：2020-02-04
申请号：US15700491
申请日：2017-09-11
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Sun-Hye Hwang , Youn-Joung Cho , Won-Woong Chung , Nam-Gun Kim , Kong-Soo Lee , Badro Im , Yoon-Chul Cho
IPC: H01L21/3213 , H01L21/311
Abstract: A method of forming a pattern includes forming an etch target layer on a substrate, forming sacrificial patterns on the etch target layer, the sacrificial patterns including a carbon-containing material, providing a silicon-sulfur compound or a sulfur-containing gas onto the sacrificial patterns to form a seed layer, providing a silicon precursor onto the seed layer to form silicon-containing mask patterns, and at least partially etching the etch target layer using the mask patterns.
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公开(公告)号：US10396083B2
公开(公告)日：2019-08-27
申请号：US15974943
申请日：2018-05-09
Applicant: Samsung Electronics Co., Ltd.
Inventor： Nam-Gun Kim , Joonkyu Rhee , Ji-Hye Lee , Chanmi Lee , Taeseop Choi
IPC: H01L21/768 , H01L27/108
Abstract: Example embodiments relate to a semiconductor device. The semiconductor device includes a substrate including an active region extending in a first direction, a plurality of bit lines running across the active region in a second direction crossing the first direction, a first spacer on a sidewall of the bit line, and a storage node contact on the active region between adjacent bit lines. The first spacer includes a first part between the storage node contact and the bit line, a second part between the first part and the storage node contact, and a third part between the first and second parts. A minimum vertical thickness of the first part is greater than a maximum vertical thickness of the third part. The maximum vertical thickness of the third part is greater than a maximum vertical thickness of the second part.
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公开(公告)号：US10153283B2
公开(公告)日：2018-12-11
申请号：US15433199
申请日：2017-02-15
Applicant: Samsung Electronics Co., Ltd.
Inventor： Nam-Gun Kim , Chanmi Lee , Joonkyu Rhee , Ji-Hye Lee , Taeseop Choi
IPC: H01L21/70 , H01L27/108 , H01L27/22 , H01L27/24
Abstract: Semiconductor devices and method of manufacturing the same are provided. The devices may include a substrate including a first impurity region and second impurity regions spaced apart from the first impurity region and a conductive line. The conductive line may extend in a first direction and may be electrically connected to the first impurity region. The devices may also include first conductive contacts on a side of the conductive line and arranged in the first direction and first insulation patterns on the side of the conductive line and arranged in the first direction. The first conductive contacts may be electrically connected to the second impurity regions. The first conductive contacts and the first insulation patterns may be alternately disposed along the first direction. Top surfaces of the first insulation patterns may be lower than a top surface of the conductive line relative to an upper surface of the substrate.
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公开(公告)号：US09875932B2
公开(公告)日：2018-01-23
申请号：US15277636
申请日：2016-09-27
Applicant: Samsung Electronics Co., Ltd.
Inventor： Nam-Gun Kim , Chan-Mi Lee
IPC: H01L21/768 , H01L21/311 , H01L27/108 , H01L27/11
CPC classification number: H01L21/76877 , H01L21/31144 , H01L21/76816 , H01L27/108 , H01L27/11 , H01L28/00
Abstract: A fabrication method of the semiconductor device comprises forming an isolation layer and an active region, which is defined by the isolation layer, on a substrate, forming an insulating layer on the substrate, forming a plurality of pillar masks, which are spaced from one another by a first gap and a second gap that is smaller than the first gap, on the insulating layer, forming spacers on the plurality of pillar masks, forming mask bridges in regions where the plurality of pillar masks are spaced from one another by the second gap by partially removing the spacers and forming a contact hole, which exposes the active region, by etching the insulating layer using the plurality of pillar masks and the mask bridges.
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公开(公告)号：US10290509B2
公开(公告)日：2019-05-14
申请号：US15443370
申请日：2017-02-27
Applicant: Samsung Electronics Co., Ltd.
Inventor： Nam-Gun Kim , Sangmin Lee , Sinhae Do , Seok-Won Cho , Taeseop Choi , Kon Ha
IPC: H01L21/311 , G03F7/20 , H01L21/033 , H01L21/308 , H01L27/108
Abstract: Example embodiments relate to a method for fabricating a semiconductor device. The method for fabricating a semiconductor device includes stacking on a substrate an etching target layer, a first mask layer, and a photoresist layer, irradiating extreme ultraviolet (EUV) radiation on the photoresist layer to form a photoresist pattern, patterning the first mask layer to form a first mask pattern using the photoresist pattern as an etching mask, and patterning the etching target layer to form a target pattern using the first mask pattern as an etching mask. The first mask layer includes at least one of a silicon layer and a titanium oxide layer.
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公开(公告)号：US10937788B2
公开(公告)日：2021-03-02
申请号：US16809913
申请日：2020-03-05
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Nam-Gun Kim , Sang-min Lee , Tae-Seop Choi , Kon Ha , Seung-jae Lee
IPC: H01L27/108 , H01L21/768 , H01L23/522 , H01L23/528 , H01L23/532
Abstract: A semiconductor device includes a substrate with an active region, a plurality of conductive line structures on the substrate, an insulating layer separating the plurality of conductive line structures from the substrate, a contact plug between every two adjacent conductive line structures, an insulating spacer structure between each conductive line structure and a corresponding contact plug, a landing pad connected to each contact plug, and a landing pad insulation pattern having an asymmetrical shape based on a vertical axis of the landing pad that extends along a normal to the substrate. The landing pad insulation pattern includes a first portion overlapping the conductive line structures and a second portion overlapping the contact plug, the first and second portions being on opposite sides of the vertical axis.
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公开(公告)号：US10573651B2
公开(公告)日：2020-02-25
申请号：US16422054
申请日：2019-05-24
Applicant: Samsung Electronics Co., Ltd.
Inventor： Nam-Gun Kim , Joonkyu Rhee , Ji-Hye Lee , Chanmi Lee , Taeseop Choi
IPC: H01L27/108 , H01L21/768
Abstract: Example embodiments relate to a semiconductor device. The semiconductor device includes a substrate including an active region extending in a first direction, a plurality of bit lines running across the active region in a second direction crossing the first direction, a first spacer on a sidewall of the bit line, and a storage node contact on the active region between adjacent bit lines. The first spacer includes a first part between the storage node contact and the bit line, a second part between the first part and the storage node contact, and a third part between the first and second parts. A minimum vertical thickness of the first part is greater than a maximum vertical thickness of the third part. The maximum vertical thickness of the third part is greater than a maximum vertical thickness of the second part.
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公开(公告)号：US09997521B2
公开(公告)日：2018-06-12
申请号：US15405808
申请日：2017-01-13
Applicant: Samsung Electronics Co., Ltd.
Inventor： Nam-Gun Kim , Joonkyu Rhee , Ji-Hye Lee , Chanmi Lee , Taeseop Choi
IPC: H01L27/108 , H01L29/76 , H01L29/94 , H01L31/119 , H01L21/768
CPC classification number: H01L27/10814 , H01L21/7682 , H01L27/10823 , H01L27/10855 , H01L27/10885 , H01L27/10888
Abstract: Example embodiments relate to a semiconductor device. The semiconductor device includes a substrate including an active region extending in a first direction, a plurality of bit lines running across the active region in a second direction crossing the first direction, a first spacer on a sidewall of the bit line, and a storage node contact on the active region between adjacent bit lines. The first spacer includes a first part between the storage node contact and the bit line, a second part between the first part and the storage node contact, and a third part between the first and second parts. A minimum vertical thickness of the first part is greater than a maximum vertical thickness of the third part. The maximum vertical thickness of the third part is greater than a maximum vertical thickness of the second part.
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公开(公告)号：US09496223B2
公开(公告)日：2016-11-15
申请号：US15071452
申请日：2016-03-16
Applicant: Samsung Electronics Co., Ltd.
Inventor： Eun-Ok Lee , Nam-Gun Kim , Gyuhwan Oh , Heesook Park , Hyun-Jung Lee , Kyungho Jang
IPC: H01L23/532
CPC classification number: H01L23/5329 , H01L21/764 , H01L21/7682 , H01L21/76831 , H01L21/76889 , H01L21/76895 , H01L21/76897 , H01L23/53209 , H01L27/10814 , H01L27/10823 , H01L27/10855 , H01L27/10876 , H01L27/10888 , H01L2924/0002 , H01L2924/00
Abstract: A spacer covering a sidewall of a contact plug includes a relatively more damaged first portion and a relatively less damaged second portion. An interface of the first and second portions of the spacer is spaced apart from a metal silicide layer of the contact plug. Thus reliability of the semiconductor device may be improved. Related fabrication methods are also described.
Abstract translation: 覆盖接触塞的侧壁的间隔件包括相对更受损的第一部分和相对较少受损的第二部分。 间隔物的第一和第二部分的界面与接触塞的金属硅化物层间隔开。 因此，可以提高半导体器件的可靠性。 还描述了相关的制造方法。
