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公开(公告)号：US20240153886A1
公开(公告)日：2024-05-09
申请号：US18225447
申请日：2023-07-24
发明人： Haseob Seong , Seungduk Baek , Ae-Nee Jang
IPC分类号： H01L23/00 , H01L23/31 , H01L23/48 , H01L25/065
CPC分类号： H01L23/562 , H01L23/3107 , H01L23/481 , H01L24/08 , H01L25/0657 , H01L2224/08146
摘要： A semiconductor package includes a substrate including a substrate pad and plural vias, the substrate having a first trench on a top surface of the substrate, and a chip stack on the substrate that includes semiconductor chips. A chip pad of a first semiconductor chip, which is a lowermost one of the semiconductor chips, is bonded to the substrate pad of the substrate. The chip pad and the substrate pad are formed of a same metallic material. The first trench overlaps with a corner of the first semiconductor chip, when viewed in plan view.
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公开(公告)号：US20240055372A1
公开(公告)日：2024-02-15
申请号：US18315689
申请日：2023-05-11
发明人： Ae-Nee Jang , Jihoon Kim , Seungduk Baek , Hyuekjae Lee
IPC分类号： H01L23/00 , H01L25/065 , H10B80/00
CPC分类号： H01L23/562 , H01L24/08 , H01L24/05 , H01L24/06 , H01L25/0657 , H10B80/00 , H01L24/94 , H01L24/80 , H01L2224/08145 , H01L2224/05647 , H01L2224/05553 , H01L2224/05555 , H01L2224/05571 , H01L2224/05582 , H01L2224/05644 , H01L2224/05666 , H01L2224/05681 , H01L2224/05686 , H01L2924/04941 , H01L2924/04953 , H01L2224/05013 , H01L2224/05147 , H01L2224/05184 , H01L2224/05009 , H01L2224/0557 , H01L2224/06181 , H01L2225/06541 , H01L2924/1431 , H01L2924/1436 , H01L2924/1437 , H01L2924/1443 , H01L2924/1438 , H01L2224/94 , H01L2224/80895
摘要： A semiconductor device includes a substrate and a lower die on the substrate. The lower die includes a first semiconductor substrate having a first device region and a first edge region therein, a first semiconductor element on the first device region, a first pad on the first device region and on the first semiconductor element, and a first interconnection structure connecting the first semiconductor element to the first pad. The first interconnection structure includes a first signal pattern on the first device region and connected to the first semiconductor element, a second signal pattern on the first device region and directly connected to the first pad, and a first dummy pattern at the same level as the second signal pattern and disposed on the first edge region. An upper die is provided, which is bonded to the lower die such that the first pad of the lower die is in contact with a second pad of the upper die.
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公开(公告)号：US11721604B2
公开(公告)日：2023-08-08
申请号：US16953745
申请日：2020-11-20
发明人： Dongjoo Choi , Seungduk Baek , Youngdeuk Kim
IPC分类号： H01L29/40 , H01L25/065 , H01L23/532 , H01L23/31 , H01L23/367 , H01L23/522
CPC分类号： H01L23/367 , H01L23/5226 , H01L25/0657 , H01L2225/06513 , H01L2225/06589
摘要： Provided is a semiconductor package including a lower semiconductor chip including a lower semiconductor substrate, a rear surface protecting layer covering a non-active surface of the lower semiconductor substrate, a plurality of lower via electrodes, and a plurality of rear surface signal pads and a plurality of rear surface thermal pads arranged on the rear surface protecting layer; an upper semiconductor chip including an upper semiconductor substrate, a wiring structure on an active surface of the upper semiconductor substrate, a front surface protecting layer that covers the wiring structure and has a plurality of front surface openings, and a plurality of signal vias and a plurality of thermal vias that fill the front surface openings; and a plurality of signal bumps connecting between the rear surface signal pads and the signal vias and a plurality of thermal bumps connecting between the rear surface thermal pads and the thermal vias.
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公开(公告)号：US20230005883A1
公开(公告)日：2023-01-05
申请号：US17857651
申请日：2022-07-05
发明人： Hyunkeun Kim , Yunrae Cho , Seungduk Baek
IPC分类号： H01L25/065 , H01L23/367 , H01L23/13 , H01L25/18 , H01L23/538
摘要： A semiconductor package is provided that includes: a package substrate; an interposer mounted on the package substrate; a first semiconductor chip mounted on the interposer; a plurality of second semiconductor chips mounted on the interposer to surround at least a portion of the first semiconductor chip; a heat radiation member arranged on the first semiconductor chip and the plurality of second semiconductor chips; and a heat blocking member extending from a portion of the heat radiation member and arranged in at least one space among a first space between the first semiconductor chip and at least one of the plurality of second semiconductor chips and a second space between at least two of the plurality of second semiconductor chips.
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公开(公告)号：US12125753B2
公开(公告)日：2024-10-22
申请号：US17584776
申请日：2022-01-26
发明人： Taehyeong Kim , Hyeongmun Kang , Seungduk Baek
IPC分类号： H01L21/66 , H01L23/00 , H01L25/065 , H01L25/10 , H01L25/18
CPC分类号： H01L22/34 , H01L24/14 , H01L24/16 , H01L24/17 , H01L25/0657 , H01L25/105 , H01L25/18 , H01L2224/1412 , H01L2224/14515 , H01L2224/16148 , H01L2224/17132 , H01L2224/17133 , H01L2224/17515 , H01L2225/06513 , H01L2225/06524 , H01L2225/06541 , H01L2225/06596 , H01L2225/1058 , H01L2924/1431 , H01L2924/1436
摘要： Disclosed is a semiconductor package comprising a first semiconductor chip and at least one second semiconductor chip on the first semiconductor chip. The second semiconductor chip includes first and second test bumps that are adjacent to an edge of the second semiconductor chip and are on a bottom surface of the second semiconductor chip. The first and second test bumps are adjacent to each other. The second semiconductor chip also includes a plurality of data bumps that are adjacent to a center of the second semiconductor chip and are on the bottom surface of the second semiconductor chip. A first interval between the second test bump and one of the data bumps is greater than a second interval between the first test bump and the second test bump. The one of the data bumps is most adjacent to the second test bump.
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公开(公告)号：US11721601B2
公开(公告)日：2023-08-08
申请号：US17095210
申请日：2020-11-11
发明人： Hyeongmun Kang , Jungmin Ko , Seungduk Baek , Taehyeong Kim , Insup Shin
IPC分类号： H01L23/24 , H01L23/31 , H01L21/56 , H01L23/538 , H01L23/00
CPC分类号： H01L23/24 , H01L21/565 , H01L23/3107 , H01L23/5385 , H01L24/13 , H01L2924/1434 , H01L2924/3511
摘要： A semiconductor package includes a substrate, a plurality of semiconductor devices stacked on the substrate, a plurality of underfill fillets disposed between the plurality of semiconductor devices and between the substrate and the plurality of semiconductor devices, and molding resin surrounding the plurality of semiconductor devices. At least one of the underfill fillets is exposed from side surfaces of the molding resin.
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公开(公告)号：US09646895B2
公开(公告)日：2017-05-09
申请号：US14714667
申请日：2015-05-18
发明人： Seungduk Baek , Ji Hwang Kim , Taeje Cho
IPC分类号： H01L21/66 , G01R31/26 , H01L23/00 , H01L23/525
CPC分类号： H01L22/14 , G01R31/2601 , H01L22/32 , H01L23/5256 , H01L24/06 , H01L2224/05554 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/73265 , H01L2924/15311 , H01L2924/00014 , H01L2924/00
摘要： A method of manufacturing a semiconductor package includes providing a semiconductor chip including a circuit pattern, a connection pad, a first test pad and a second test pad, each of the connection pad, the first test pad and the second test pad respectively electrically connected to the circuit pattern, evaluating electrical characteristics of the semiconductor chip by applying a first test voltage to the first test pad and a second test voltage to the second test pad, the second test voltage being higher than the first test voltage, and electrically disconnecting the second test pad from the circuit pattern.
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公开(公告)号：US20240030074A1
公开(公告)日：2024-01-25
申请号：US18320046
申请日：2023-05-18
发明人： Minki Kim , Seungduk Baek , Hyuekjae Lee
IPC分类号： H01L21/66 , H01L23/00 , H01L25/065
CPC分类号： H01L22/32 , H01L24/06 , H01L24/80 , H01L25/0657 , H01L2224/0603 , H01L2225/06596 , H01L2224/80345
摘要： A semiconductor device includes a base structure comprising a first bonding pad and a first test pad, and a semiconductor chip comprising a second bonding pad being in contact with the first bonding pad of the base structure and a second test pad being in contact with the first test pad of the base structure. A width of the second bonding pad of the semiconductor chip is less than a width of the second test pad of the semiconductor chip. An air gap is provided between the first test pad of the base structure and the second test pad of the semiconductor chip.
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公开(公告)号：US20230378110A1
公开(公告)日：2023-11-23
申请号：US18067773
申请日：2022-12-19
发明人： MINKI KIM , Seungduk Baek , Hyuekjae Lee
CPC分类号： H01L24/08 , H10B80/00 , H01L24/03 , H01L24/05 , H01L24/80 , H01L2924/1438 , H01L2924/1431 , H01L2224/0801 , H01L2224/08056 , H01L2224/08055 , H01L2224/0807 , H01L2224/08059 , H01L2224/08058 , H01L2224/08121 , H01L2224/08145 , H01L2224/08225 , H01L2224/05647 , H01L2224/05687 , H01L2224/80895 , H01L2224/80896 , H01L2224/03831 , H01L2224/0384
摘要： Provided is a semiconductor device including lower and upper structures. The lower structure includes a first substrate, a first pad on the first substrate, and a first insulating layer surrounding the first pad. The upper structure includes a second substrate, a second pad on the second substrate, and a second insulating layer surrounding the second pad. The upper and lower structures contact each other. The first and second pads contact each other. The first and second insulating layers contact each other. The first insulating layer includes a first recess adjacent the first pad, the second insulating layer includes a second recess that is adjacent the second pad and overlaps the first recess, and a cavity is defined by the first recess and the second recess, and particles of a metallic material constituting the first and second pads are in the cavity.
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公开(公告)号：US20230163087A1
公开(公告)日：2023-05-25
申请号：US17944430
申请日：2022-09-14
发明人： Minki Kim , Seungduk Baek , Won IL Lee
IPC分类号： H01L23/00 , H01L25/065
CPC分类号： H01L24/05 , H01L25/0657 , H01L24/08 , H01L2225/06527 , H01L2225/06544 , H01L2224/08145 , H01L2924/3512 , H01L2224/05541 , H01L2224/05551 , H01L2224/05557 , H01L2224/05558 , H01L2224/05576 , H01L2224/05647 , H01L2224/05687 , H01L2224/05009 , H01L2224/05011 , H01L2224/05017 , H01L2224/05018 , H01L2224/05025 , H01L2224/05076 , H01L2224/05083 , H01L2224/05166 , H01L2224/05181 , H01L2224/05187 , H01L2224/0239 , H01L2224/02331 , H01L2224/02381 , H01L2924/1434 , H01L2924/1431
摘要： A semiconductor package includes: a semiconductor substrate; a through electrode that penetrates the semiconductor substrate; a first pad disposed on the through electrode; and a dielectric structure disposed on the semiconductor substrate, wherein a lower portion of the dielectric structure at least partially surrounds the through electrode, wherein an upper portion of the dielectric structure at least partially surrounds the first pad, wherein the dielectric structure includes: a first dielectric pattern; an etch stop pattern disposed on the first dielectric pattern; and a second dielectric pattern spaced apart from the first dielectric pattern by the etch stop pattern, wherein the first pad is in contact with the through electrode, the first dielectric pattern, the etch stop pattern, and second dielectric pattern, and wherein a top surface of the through electrode is at a level higher than a level of a top surface of the first dielectric pattern.
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