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    System and method for compact neural network modeling of transistors
    6.
    发明授权
    System and method for compact neural network modeling of transistors 有权

    公开(公告)号：US11537841B2

    公开(公告)日：2022-12-27

    申请号：US16430219

    申请日：2019-06-03

    申请人： Samsung Electronics Co., Ltd.

    发明人： Jing Wang ,  Woosung Choi

    IPC分类号： G06N3/04 ,  G06F119/12 ,  G06N3/08 ,  G06F30/33

    摘要： A method for generating a model of a transistor includes: initializing hyper-parameters; training the neural network in accordance with the hyper-parameters and training data relating transistor input state values to transistor output state values to compute neural network parameters; determining whether the transistor output state values of the training data match an output of the neural network; porting the neural network to a circuit simulation code to generate a ported neural network; simulating a test circuit using the ported neural network to simulate behavior of a transistor of the test circuit to generate simulation output; determining whether a turnaround time of the generation of the simulation output is satisfactory; in response to determining that the turnaround time is unsatisfactory, re-training the neural network based on updated hyper-parameters; and in response to determining that the turnaround time is satisfactory, outputting the ported neural network as the model of the transistor.

    SYSTEMS, METHODS, AND COMPUTER PROGRAM PRODUCTS FOR TRANSISTOR COMPACT MODELING USING ARTIFICIAL NEURAL NETWORKS
    7.
    发明申请
    SYSTEMS, METHODS, AND COMPUTER PROGRAM PRODUCTS FOR TRANSISTOR COMPACT MODELING USING ARTIFICIAL NEURAL NETWORKS 有权

    公开(公告)号：US20220114317A1

    公开(公告)日：2022-04-14

    申请号：US17465361

    申请日：2021-09-02

    申请人： Samsung Electronics Co., Ltd.

    发明人： Jing Wang ,  Woosung Choi

    IPC分类号： G06F30/367 ,  G06N3/08

    摘要： A computer implemented method for determining performance of a semiconductor device is provided. The method includes providing training data comprising input state values and training capacitance values to a neural network executing on a computer system; processing the input state values through the neural network to generate modeled charge values; converting the modeled charge values to modeled capacitance values; determining, by the computer system, whether the training capacitance values of the training data are within a threshold value of the modeled capacitance values utilizing a loss function that omits the modeled charge values; and in response to determining that the training capacitance values of the training data are within the threshold value of the modeled capacitance values, converting, by the computer system, the neural network to a circuit simulation code to generate a converted neural network.

    SYSTEM AND METHOD FOR COMPACT NEURAL NETWORK MODELING OF TRANSISTORS
    8.
    发明申请
    SYSTEM AND METHOD FOR COMPACT NEURAL NETWORK MODELING OF TRANSISTORS 审中-公开

    公开(公告)号：US20200320366A1

    公开(公告)日：2020-10-08

    申请号：US16430219

    申请日：2019-06-03

    申请人： Samsung Electronics Co., Ltd.

    发明人： Jing Wang ,  Woosung Choi

    IPC分类号： G06N3/04 ,  G06F17/50 ,  G06N3/08

    摘要： A method for generating a model of a transistor includes: initializing hyper-parameters; training the neural network in accordance with the hyper-parameters and training data relating transistor input state values to transistor output state values to compute neural network parameters; determining whether the transistor output state values of the training data match an output of the neural network; porting the neural network to a circuit simulation code to generate a ported neural network; simulating a test circuit using the ported neural network to simulate behavior of a transistor of the test circuit to generate simulation output; determining whether a turnaround time of the generation of the simulation output is satisfactory; in response to determining that the turnaround time is unsatisfactory, re-training the neural network based on updated hyper-parameters; and in response to determining that the turnaround time is satisfactory, outputting the ported neural network as the model of the transistor.

    IMPORTANCE SAMPLING METHOD FOR MULTIPLE FAILURE REGIONS
    9.
    发明申请
    IMPORTANCE SAMPLING METHOD FOR MULTIPLE FAILURE REGIONS 审中-公开

    公开(公告)号：US20190265296A1

    公开(公告)日：2019-08-29

    申请号：US16406868

    申请日：2019-05-08

    申请人： Samsung Electronics Co., Ltd.

    发明人： Nuo Xu ,  Jing Wang ,  Woosung Choi

    IPC分类号： G01R31/317 ,  G01R31/3193 ,  G01R31/3177

    摘要： In a method of circuit yield analysis, the method includes: detecting a plurality of failed samples respectively located at a plurality of failure regions in a multi-dimensional parametric space; clustering the failed samples to identify the failure regions; filtering features of the failed samples to determine a parameter component that is a non-principal component in affecting circuit yield; applying a dimensional reduction method on a dimension corresponding to the parameter component; and constructing a final importance sampling (IS) distribution function using a mixed Gaussian (mGaussian) function corresponding to all of the failure regions containing a rare failure event.