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公开(公告)号：US10224104B2
公开(公告)日：2019-03-05
申请号：US15078555
申请日：2016-03-23
发明人： Murshed Chowdhury , Jin Liu , Yanli Zhang , Andrew Lin , Raghuveer S. Makala , Johann Alsmeier
IPC分类号： G11C16/10 , G11C16/26 , G11C16/04 , H01L27/11582 , H01L27/11524 , H01L27/11556 , H01L27/1157
摘要： Two vertical NAND strings can share a common bit line by providing two pairs of drain select transistors. Channels of each vertical NAND string containing an adjoining pair of drain select transistors are incorporated into a respective vertical semiconductor channel, which is adjoined to a respective drain region which is connected to the common bit line. The drain select transistors have mismatched threshold voltages at each level such that each vertical NAND string includes a level at which a respective drain select transistor has a higher threshold voltage than a counterpart drain select transistor for the other vertical NAND string at the same level. By turning on three drain select transistors out of four, only one vertical NAND string can be activated while the common bit line is biased at a suitable bias voltage. A programming operation or a read operation can be performed only on the activated NAND string.
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公开(公告)号：US09799670B2
公开(公告)日：2017-10-24
申请号：US15017961
申请日：2016-02-08
发明人： Masatoshi Nishikawa , Jin Liu , Chun Ge , Yanli Zhang
IPC分类号： H01L27/115 , H01L29/792 , H01L21/28 , H01L27/1157 , H01L27/11582 , H01L27/11573
CPC分类号： H01L27/1157 , H01L21/28282 , H01L27/11565 , H01L27/11573 , H01L27/11575 , H01L27/11582 , H01L29/7926
摘要： A three-dimensional memory device includes an alternating stack of electrically conductive layers and insulating layers located over a substrate, an array of memory stack structures, each memory stack structure extending through the alternating stack and including a memory film and a semiconductor channel laterally surrounded by the memory film, and an array of dielectric pillars located between the alternating stack and the substrate.
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3.发明授权Multilevel memory stack structure with joint electrode having a collar portion and methods for manufacturing the same 有权具有具有套环部分的接合电极的多层存储器堆叠结构及其制造方法公开(公告)号：US09570463B1
公开(公告)日：2017-02-14
申请号：US14883966
申请日：2015-10-15
发明人： Yanli Zhang , Raghuveer S. Makala , Jin Liu , Murshed Chowdhury , Yao-Sheng Lee , Johann Alsmeier
IPC分类号： H01L27/115
CPC分类号： H01L27/11582 , H01L27/1157 , H01L27/11573 , H01L27/11575
摘要： A three-dimensional memory device including multiple stack structures can be formed with a joint region electrode, which is an electrode formed at a joint region located near the interface between an upper stack structure and a lower stack structure. A memory stack structure is formed through the multiple stack structures. The joint region electrode laterally surrounds a portion of the memory stack structure in proximity to the interface between different stack structures. The joint region electrode includes a layer portion having a thickness and a collar portion that laterally surrounds the memory stack structure and having a greater vertical extent than the thickness of the layer portion. The increased vertical extent of the collar portion with respect to the vertical extent of the layer portion provides enhanced control of a portion of a semiconductor channel in the memory stack structure located near the interface between different stack structures.
摘要翻译： 包括多个堆叠结构的三维存储器件可以形成有接合区域电极，该接合区域电极是形成在位于上部堆叠结构和下部堆叠结构之间的界面附近的接合区域处的电极。 通过多个堆叠结构形成存储器堆叠结构。 接合区域电极在不同的堆叠结构之间的界面附近横向地围绕存储器堆叠结构的一部分。 接合区域电极包括具有厚度的层部分和环形部分，该部分横向包围存储器堆叠结构并且具有比层部分的厚度更大的垂直范围。 套环部分相对于层部分的垂直范围增加的垂直范围提供对位于不同堆叠结构之间的界面附近的存储器堆叠结构中的半导体通道的一部分的增强的控制。
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4.发明授权Three dimensional NAND device having nonlinear control gate electrodes and method of making thereof 有权具有非线性控制栅电极的三维NAND器件及其制造方法公开(公告)号：US09455267B2
公开(公告)日：2016-09-27
申请号：US14491315
申请日：2014-09-19
发明人： Yanli Zhang , Johann Alsmeier
IPC分类号： H01L23/528 , H01L21/283 , H01L21/768 , H01L21/31 , H01L27/115 , H01L29/792 , H01L29/423 , H01L29/417 , H01L29/06 , H01L21/3213 , H01L21/02 , H01L21/28 , H01L29/788 , H01L29/66 , H01L21/8234 , G11C16/06 , G11C16/04
CPC分类号： H01L27/11582 , G11C16/0483 , G11C16/06 , H01L21/02365 , H01L21/28273 , H01L21/28282 , H01L21/283 , H01L21/31 , H01L21/32133 , H01L21/768 , H01L21/823412 , H01L21/823418 , H01L21/823468 , H01L21/823475 , H01L21/823487 , H01L23/528 , H01L27/11519 , H01L27/11521 , H01L27/11556 , H01L27/11565 , H01L27/11568 , H01L29/0657 , H01L29/41775 , H01L29/42328 , H01L29/42336 , H01L29/42344 , H01L29/42352 , H01L29/66825 , H01L29/66833 , H01L29/7889 , H01L29/7926 , H01L2924/0002 , H01L2924/00
摘要： A monolithic three dimensional NAND string includes a plurality of control gate electrodes extending substantially parallel to a major surface of a substrate in at least one active region, a plurality of semiconductor channels having at least one end portion of each of the plurality of semiconductor channels extending substantially perpendicular to the major surface of the substrate, at least one memory film located between each of the plurality of control gate electrodes and each respective semiconductor channel of the plurality of semiconductor channels, and at least one first slit trench extending substantially perpendicular to the major surface of the substrate. Each of the plurality of control gate electrodes has a nonlinear side wall adjacent to the at least one first slit trench in the at least one active region.
摘要翻译： 单片三维NAND串包括在至少一个有源区域中基本上平行于衬底的主表面延伸的多个控制栅电极，多个半导体沟道具有多个半导体沟道中的每一个的至少一个端部延伸 基本上垂直于衬底的主表面，位于多个控制栅电极中的每一个和多个半导体沟道中的每个相应半导体沟道之间的至少一个存储膜，以及至少一个基本上垂直于主体的第一狭缝沟槽 基板的表面。 多个控制栅极电极中的每一个具有与至少一个有源区域中的至少一个第一狭缝沟槽相邻的非线性侧壁。
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5.发明授权Three dimensional NAND device with channel contacting conductive source line and method of making thereof 有权具有通道接触导电源线的三维NAND器件及其制造方法公开(公告)号：US09455263B2
公开(公告)日：2016-09-27
申请号：US14317274
申请日：2014-06-27
发明人： Yanli Zhang , Go Shoji , Johann Alsmeier , Jayavel Pachamuthu , Yingda Dong , Jiahui Yuan
IPC分类号： H01L21/70 , H01L21/336 , H01L27/115
CPC分类号： H01L27/11582 , H01L21/28282 , H01L27/11529 , H01L27/11556 , H01L27/11565 , H01L27/1157 , H01L29/7883
摘要： A NAND memory cell region of a NAND device includes a conductive source line that extends substantially parallel to a major surface of a substrate, a first semiconductor channel that extends substantially perpendicular to a major surface of the substrate, and a second semiconductor channel that extends substantially perpendicular to the major surface of the substrate. At least one of a bottom portion and a side portion of the first semiconductor channel contacts the conductive source line and at least one of a bottom portion and a side portion of the second semiconductor channel contacts the conductive source line.
摘要翻译： NAND器件的NAND存储器单元区域包括基本上平行于衬底的主表面延伸的导电源线，基本上垂直于衬底的主表面延伸的第一半导体沟道，以及基本上延伸 垂直于基片的主表面。 第一半导体沟道的底部和侧部中的至少一个与导电源线接触，并且第二半导体沟道的底部和侧部中的至少一个与导电源线接触。
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公开(公告)号：US09379132B2
公开(公告)日：2016-06-28
申请号：US14523287
申请日：2014-10-24
发明人： Sateesh Koka , Raghuveer S. Makala , Yanli Zhang , Senaka Kanakamedala , Rahul Sharangpani , Yao-Sheng Lee , George Matamis
CPC分类号： H01L27/11582 , H01L27/11519 , H01L27/11524 , H01L27/11556 , H01L27/11565 , H01L27/1157 , H01L29/66666 , H01L29/66825 , H01L29/66833 , H01L29/7889 , H01L29/7926
摘要： Methods of making monolithic three-dimensional memory devices include performing a first etch to form a memory opening and a second etch using a different etching process to remove a damaged portion of the semiconductor substrate from the bottom of the memory opening. A single crystal semiconductor material is formed over the substrate in the memory opening using an epitaxial growth process. Additional embodiments include improving the quality of the interface between the semiconductor channel material and the underlying semiconductor layers in the memory opening which may be damaged by the bottom opening etch, including forming single crystal semiconductor channel material by epitaxial growth from the bottom surface of the memory opening and/or oxidizing surfaces exposed to the bottom opening etch and removing the oxidized surfaces prior to forming the channel material. Monolithic three-dimensional memory devices formed by the embodiment methods are also disclosed.
摘要翻译： 制造单片三维存储器件的方法包括执行第一蚀刻以形成存储器开口和使用不同蚀刻工艺的第二蚀刻，以从存储器开口的底部去除半导体衬底的损坏部分。 使用外延生长工艺在存储器开口中的衬底上形成单晶半导体材料。 另外的实施例包括提高存储器开口中的半导体沟道材料和底层半导体层之间的界面的质量，这可能被底部开口蚀刻损坏，包括通过从存储器的底表面的外延生长形成单晶半导体沟道材料 暴露于底部开口蚀刻的开口和/或氧化表面，并在形成沟道材料之前去除氧化的表面。 还公开了通过实施方式形成的单片三维存储器件。
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公开(公告)号：US20150380424A1
公开(公告)日：2015-12-31
申请号：US14319591
申请日：2014-06-30
发明人： Raghuveer S. Makala , Yao-Sheng Lee , Senaka Krishna Kanakamedala , Yanli Zhang , George Matamis , Johann Alsmeier
IPC分类号： H01L27/115 , H01L21/02 , H01L21/28 , H01L21/285 , H01L29/49 , H01L29/51
CPC分类号： H01L27/11556 , H01L21/02123 , H01L21/02164 , H01L21/0217 , H01L21/02186 , H01L21/28273 , H01L21/28556 , H01L21/28568 , H01L27/11519 , H01L27/11524 , H01L27/11526 , H01L29/42324 , H01L29/495 , H01L29/511 , H01L29/518 , H01L29/7827
摘要： A method of making a three dimensional NAND string includes providing a stack of alternating first material layers and second material layers over a substrate. The method further includes forming a front side opening in the stack, forming a tunnel dielectric in the front side opening, forming a semiconductor channel in the front side opening over the tunnel dielectric and forming a back side opening in the stack. The method also includes selectively removing the second material layers through the back side opening to form back side recesses between adjacent first material layers, forming a metal charge storage layer in the back side opening and in the back side recesses and forming discrete charge storage regions in the back side recesses by removing the metal charge storage layer from the back side opening and selectively recessing the metal charge storage layer in the back side recesses.
摘要翻译： 制造三维NAND串的方法包括在衬底上提供交替的第一材料层和第二材料层的堆叠。 该方法还包括在堆叠中形成前侧开口，在前侧开口中形成隧道电介质，在隧道电介质的前侧开口形成半导体沟道，并在叠层中形成背面开口。 该方法还包括通过后侧开口选择性地去除第二材料层，以在相邻的第一材料层之间形成背侧凹槽，在后侧开口和后侧凹槽中形成金属电荷存储层，并在后侧凹槽中形成离散电荷存储区域 通过从后侧开口去除金属电荷存储层并选择性地使金属电荷存储层在后侧凹部中凹陷来使背面凹陷。
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8.发明申请公开(公告)号：US20170278571A1
公开(公告)日：2017-09-28
申请号：US15078555
申请日：2016-03-23
发明人： Murshed Chowdhury , Jin Liu , Yanli Zhang , Andrew Lin , Raghuveer S. Makala , Johann Alsmeier
CPC分类号： G11C16/0483 , G11C16/10 , G11C16/26 , H01L27/11524 , H01L27/11556 , H01L27/1157 , H01L27/11582
摘要： Two vertical NAND strings can share a common bit line by providing two pairs of drain select transistors. Channels of each vertical NAND string containing an adjoining pair of drain select transistors are incorporated into a respective vertical semiconductor channel, which is adjoined to a respective drain region which is connected to the common bit line. The drain select transistors have mismatched threshold voltages at each level such that each vertical NAND string includes a level at which a respective drain select transistor has a higher threshold voltage than a counterpart drain select transistor for the other vertical NAND string at the same level. By turning on three drain select transistors out of four, only one vertical NAND string can be activated while the common bit line is biased at a suitable bias voltage. A programming operation or a read operation can be performed only on the activated NAND string.
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公开(公告)号：US09627399B2
公开(公告)日：2017-04-18
申请号：US14808229
申请日：2015-07-24
IPC分类号： H01L27/115 , H01L27/11578 , H01L27/1157 , H01L29/423 , H01L29/66 , H01L29/792 , H01L27/02
CPC分类号： H01L27/11578 , H01L21/28282 , H01L27/0207 , H01L27/11565 , H01L27/1157 , H01L27/11582 , H01L29/4234 , H01L29/42344 , H01L29/66833 , H01L29/7926
摘要： An alternating stack of insulating layers and sacrificial material layers is formed on a substrate. Separator insulator structures can be optionally formed through the alternating stack. Memory opening are formed through the alternating stack, and the sacrificial material layers are removed selective to the insulating layers. Electrically conductive layers are formed in the lateral recesses by deposition of at least one conductive material. Metal-semiconductor alloy regions are appended to the electrically conductive layers by depositing at least a semiconductor material and inducing reaction of the semiconductor material with the material of the electrically conductive layers and/or a sacrificial metal layer. Memory stack structures can be formed in the memory openings and directly on the metal-semiconductor alloy regions of the electrically conductive layers.
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10.发明授权公开(公告)号：US09627395B2
公开(公告)日：2017-04-18
申请号：US14619691
申请日：2015-02-11
IPC分类号： H01L27/115 , H01L21/324 , H01L21/768 , H01L21/28 , H01L23/522 , H01L29/788 , H01L27/11556
CPC分类号： H01L27/11556 , H01L21/28273 , H01L21/76802 , H01L21/76877 , H01L27/11524 , H01L27/1157 , H01L27/11582 , H01L29/7883
摘要： A stack including an alternating plurality of first material layers and second material layers is provided. A memory opening is formed and at least a contiguous semiconductor material portion including a semiconductor channel is formed therein. The contiguous semiconductor material portion includes an amorphous or polycrystalline semiconductor material. A metallic material portion is provided at a bottom surface of the semiconductor channel, at a top surface of the semiconductor channel, or on portions of an outer sidewall surface of the semiconductor channel. An anneal is performed to induce diffusion of a metal from the metallic material portion through the semiconductor channel, thereby inducing conversion of the amorphous or polycrystalline semiconductor material into a crystalline semiconductor material. The crystalline semiconductor material has a relatively large grain size due to the catalytic crystallization process, and can provide enhanced charge carrier mobility.
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