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公开(公告)号：US10861508B1
公开(公告)日：2020-12-08
申请号：US16679528
申请日：2019-11-11
Applicant: SanDisk Technologies LLC
Inventor： Shiv Mathur , Nitin Gupta , Ramakrishnan Subramanian
IPC: G11C7/22 , G11C7/10 , G06F9/30 , G11C11/4096
Abstract: A methodology and structure for a encoding a data stat signal in the data lock signal, e.g., the data strobe signal such as DBQ. The data strobe signal can maintain the clock continuity, e.g., the rise and fall edges are at the timing signal, and the data inversion can be based on the amplitude of the data strobe signal. This allows the data set on the data lines, e.g., D0-D7, to either be non-inverted or inverted, to save power consumed in the memory device.
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公开(公告)号：US11984168B2
公开(公告)日：2024-05-14
申请号：US17835324
申请日：2022-06-08
Applicant: SanDisk Technologies LLC
Inventor： Nitin Gupta , Shiv Harit Mathur , Ramakrishnan Subramanian , Dmitry Vaysman
CPC classification number: G11C16/30 , G11C7/1096 , G11C11/1697
Abstract: An interface circuit that can operate in toggle mode at data high transfer rates while reducing the self-induced noise is presented. The high speed toggle mode interface supplies a data signal to a data line or other transfer line by a driver circuit. The driver circuit includes a pair of series connected transistors connected between a high supply level and a low supply level, where the data line is supplied from a node between the two transistors. A resistor is connected between one or both of the transistors and one of the supply levels, with a capacitor connected between the low supply level and a node between the resistor and the transistor. The resistor helps to isolate the transistor from the supply level while the capacitor can act as current reservoir to boost the current to the transistor during data transition, reducing the noise seen by the voltage supply.
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公开(公告)号：US20230402107A1
公开(公告)日：2023-12-14
申请号：US17835324
申请日：2022-06-08
Applicant: SanDisk Technologies LLC
Inventor： Nitin Gupta , Shiv Harit Mathur , Ramakrishnan Subramanian , Dmitry Vaysman
CPC classification number: G11C16/30 , G11C11/1697
Abstract: An interface circuit that can operate in toggle mode at data high transfer rates while reducing the self-induced noise is presented. The high speed toggle mode interface supplies a data signal to a data line or other transfer line by a driver circuit. The driver circuit includes a pair of series connected transistors connected between a high supply level and a low supply level, where the data line is supplied from a node between the two transistors. A resistor is connected between one or both of the transistors and one of the supply levels, with a capacitor connected between the low supply level and a node between the resistor and the transistor. The resistor helps to isolate the transistor from the supply level while the capacitor can act as current reservoir to boost the current to the transistor during data transition, reducing the noise seen by the voltage supply.
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公开(公告)号：US11210241B1
公开(公告)日：2021-12-28
申请号：US17068957
申请日：2020-10-13
Applicant: SANDISK TECHNOLOGIES LLC
Inventor： Nitin Gupta , Ashish Savadia , Jayanth Thimmaiah , Ramakrishnan Subramanian , Rampraveen Somasundaram , Shiv Harit Mathur , Vinayak Ghatawade , Siddesh Darne , Venkatesh Ramachandra , Elkana Richter
Abstract: A data storage system includes a storage medium including plurality of memory cells, a storage controller in communication with the storage medium, an electrical interface circuitry configured to pass data via a channel disposed between the storage medium and the storage controller; and voltage training circuitry configured to train a high-level output voltage (VOH) for each of a plurality of data lines of the channel. Training the VOH includes, for each of the plurality of data lines of the channel, calibrating a pull-up driver of the storage controller against an on-die termination circuit of the storage medium, calibrating a pull-down driver of the storage controller against the pull-up driver of the storage controller, and calibrating an on-die termination circuit of the storage controller against a pull-up driver of the storage medium.
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公开(公告)号：US11079824B2
公开(公告)日：2021-08-03
申请号：US16390821
申请日：2019-04-22
Applicant: SanDisk Technologies LLC
Inventor： Nitin Gupta , Bhavin Odedara , Raghu Voleti
IPC: G06F1/00 , G06F11/30 , G06F1/28 , G05F1/46 , G01R19/165
Abstract: Systems and methods for power distribution are disclosed. A system includes a first power domain that supplies current to an integrated circuit at a first voltage level, a second power domain that supplies current to the integrated circuit at a second voltage level, and a current distribution component that is connected to the first power domain and connectable to the second power domain and senses a metric comprising a first current level or a first voltage level drawn from the first power domain, determines whether the metric exceeds a first threshold, and in response to determining that the metric exceeds the first threshold, electrically connects the second power domain to the integrated circuit to supply additional current such that an aggregate current level received by the integrated circuit comprises current from the first power domain and the additional current from the second power domain.
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公开(公告)号：US20180173619A1
公开(公告)日：2018-06-21
申请号：US15491917
申请日：2017-04-19
Applicant: SanDisk Technologies LLC
Inventor： Vijay Sivasankaran , Srinivasa Rao Sabbineni , Saugata Das , Indraneel Mukherjee , Nitin Gupta
CPC classification number: G06F12/0246 , G06F3/061 , G06F3/0631 , G06F3/0659 , G06F3/0679 , G06F2212/1016 , G06F2212/7201 , G06F2212/7205
Abstract: In a storage device having a storage controller and multiple memory channels, each memory channel has a memory channel controller. The storage controller, in response to a host command to perform a respective read operation at a logical address specified by the host command, identifies the memory channel based on the specified logical address, and also identifies a portion of logical to physical address mapping information corresponding to the logical address. The storage controller sends to a controller of the identified memory channel a read command that includes information identifying the portion of logical to physical address mapping information corresponding to the logical address. Using that information, the memory channel controller translates the logical address into a physical address and reads data from the physical address.
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公开(公告)号：US20180302093A1
公开(公告)日：2018-10-18
申请号：US15626580
申请日：2017-06-19
Applicant: SanDisk Technologies LLC
Inventor： Shiv Harit Mathur , Anand Sharma , Ramakrishnan Karungulam Subramanian , Nitin Gupta
IPC: H03K19/0185 , H03K19/21
Abstract: A circuit may receive control signals to generate an output signal with pulses corresponding to pulses of a source signal. The circuit may include a primary circuit and an auxiliary circuit. The primary circuit may constantly participate in the generation of pulses of the output signal. The auxiliary circuit may selectively participate with the primary circuit in the generation of the pulses. For two consecutive pulses of the output signal, whether the auxiliary circuit participates in generating the latter of the two pulses may depend on whether a threshold level is crossed during generation of the consecutive pulses.
