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公开(公告)号：US20180190677A1
公开(公告)日：2018-07-05
申请号：US15897318
申请日：2018-02-15
Applicant: Semiconductor Energy Laboratory Co., Ltd.
Inventor： Atsuo ISOBE , Shunpei YAMAZAKI , Koji DAIRIKI , Hiroshi SHIBATA , Chiho KOKUBO , Tatsuya ARAO , Masahiko HAYAKAWA , Hidekazu MIYAIRI , Akihisa SHIMOMURA , Koichiro TANAKA , Mai AKIBA
IPC: H01L27/12 , B23K26/073 , H01L21/02 , H01L21/20 , H01L21/3213 , H01L21/84 , H01L29/66 , H01L29/786
CPC classification number: H01L27/1222 , B23K26/0738 , H01L21/02354 , H01L21/02356 , H01L21/02675 , H01L21/02683 , H01L21/02686 , H01L21/02691 , H01L21/2026 , H01L21/32139 , H01L21/84 , H01L27/1214 , H01L27/1218 , H01L27/124 , H01L27/1255 , H01L27/1274 , H01L27/1281 , H01L27/1296 , H01L29/66757 , H01L29/78603 , H01L29/78675 , H01L29/78696 , Y10S118/90 , Y10T117/10 , Y10T117/1004 , Y10T117/1008
Abstract: A semiconductor device production system using a laser crystallization method is provided which can avoid forming grain boundaries in a channel formulation region of a TFT, thereby preventing grain boundaries from lowering the mobility of the TFT greatly, from lowering ON current, and from increasing OFF current. Rectangular or stripe pattern depression and projection portions are formed on an insulating film. A semiconductor film is formed on the insulating film. The semiconductor film is irradiated with continuous wave laser light by running the laser light along the stripe pattern depression and projection portions of the insulating film or along the major or minor axis direction of the rectangle. Although continuous wave laser light is most preferred among laser light, it is also possible to use pulse oscillation laser light in irradiating the semiconductor film.
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公开(公告)号：US20160204268A1
公开(公告)日：2016-07-14
申请号：US15049761
申请日：2016-02-22
Applicant: Semiconductor Energy Laboratory Co., Ltd.
Inventor： Takehisa HATANO , Sachiaki TEZUKA , Atsuo ISOBE
IPC: H01L29/786 , H01L29/04 , H01L27/12 , H01L29/24 , H01L29/423
CPC classification number: H01L29/66969 , H01L21/0334 , H01L21/467 , H01L27/1156 , H01L27/1207 , H01L27/1225 , H01L29/045 , H01L29/24 , H01L29/42364 , H01L29/42384 , H01L29/78603 , H01L29/7869
Abstract: A semiconductor device which is miniaturized while favorable characteristics thereof are maintained is provided. In addition, the miniaturized semiconductor device is provided with a high yield. The semiconductor device has a structure including an oxide semiconductor film provided over a substrate having an insulating surface; a source electrode layer and a drain electrode layer which are provided in contact with side surfaces of the oxide semiconductor film and have a thickness larger than that of the oxide semiconductor film; a gate insulating film provided over the oxide semiconductor film, the source electrode layer, and the drain electrode layer; and a gate electrode layer provided in a depressed portion formed by a step between a top surface of the oxide semiconductor film and top surfaces of the source electrode layer and the drain electrode layer.
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公开(公告)号：US20160093642A1
公开(公告)日：2016-03-31
申请号：US14961061
申请日：2015-12-07
Applicant: Semiconductor Energy Laboratory Co., Ltd.
Inventor： Atsuo ISOBE , Yutaka OKAZAKI , Kazuya HANAOKA , Shinya SASAGAWA , Motomu KURATA
IPC: H01L27/12 , H01L27/115 , H01L29/417 , H01L29/10 , H01L29/24 , H01L29/786
CPC classification number: H01L27/1225 , H01L27/10879 , H01L27/1104 , H01L27/11521 , H01L27/124 , H01L27/1248 , H01L29/1033 , H01L29/24 , H01L29/41733 , H01L29/41775 , H01L29/66742 , H01L29/66969 , H01L29/78 , H01L29/7869
Abstract: A first conductive film overlapping with an oxide semiconductor film is formed over a gate insulating film, a gate electrode is formed by selectively etching the first conductive film using a resist subjected to electron beam exposure, a first insulating film is formed over the gate insulating film and the gate electrode, removing a part of the first insulating film while the gate electrode is not exposed, an anti-reflective film is formed over the first insulating film, the anti-reflective film, the first insulating film and the gate insulating film are selectively etched using a resist subjected to electron beam exposure, and a source electrode in contact with one end of the oxide semiconductor film and one end of the first insulating film and a drain electrode in contact with the other end of the oxide semiconductor film and the other end of the first insulating film are formed.
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公开(公告)号：US20150372123A1
公开(公告)日：2015-12-24
申请号：US14837565
申请日：2015-08-27
Applicant: Semiconductor Energy Laboratory Co., Ltd.
Inventor： Shunpei YAMAZAKI , Atsuo ISOBE , Yoshinori IEDA , Masaharu NAGAI
IPC: H01L29/66 , H01L29/786 , H01L29/417
CPC classification number: H01L29/66969 , H01L29/41733 , H01L29/66742 , H01L29/786 , H01L29/7869
Abstract: A semiconductor device including a minute transistor with a short channel length is provided. A gate insulating layer is formed over a gate electrode layer; an oxide semiconductor layer is formed over the gate insulating layer; a first conductive layer and a second conductive layer are formed over the oxide semiconductor layer; a conductive film is formed over the first conductive layer and the second conductive layer; a resist mask is formed over the conductive film by performing electron beam exposure; and then a third conductive layer and a fourth conductive layer are formed over and in contact with the first conductive layer and the second conductive layer, respectively, by selectively etching the conductive film.
Abstract translation: 提供了包括具有短沟道长度的微小晶体管的半导体器件。 在栅电极层上形成栅极绝缘层; 在栅绝缘层上形成氧化物半导体层; 在所述氧化物半导体层上形成第一导电层和第二导电层; 在第一导电层和第二导电层上形成导电膜; 通过进行电子束曝光在导电膜上形成抗蚀剂掩模; 然后通过选择性地蚀刻导电膜，分别在第一导电层和第二导电层上形成第三导电层和第四导电层，并与第二导电层接触。
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公开(公告)号：US20150049278A1
公开(公告)日：2015-02-19
申请号：US14527020
申请日：2014-10-29
Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
Inventor： Hiroshi SHIBATA , Atsuo ISOBE
IPC: G02F1/1362 , G02F1/1333 , G02F1/1368
CPC classification number: H01L27/1255 , G02F1/133345 , G02F1/13454 , G02F1/136209 , G02F1/136213 , G02F1/136227 , G02F1/136277 , G02F1/136286 , G02F1/1368 , H01L27/12 , H01L27/1214 , H01L27/124 , H01L27/3244 , H01L27/3248 , H01L27/3262 , H01L27/3265 , H01L27/3276 , H01L29/4908 , H01L29/786 , H01L29/78633
Abstract: To provide a liquid crystal display device having high quality display by obtaining a high aperture ratio while securing a sufficient storage capacitor (Cs), and at the same time, by dispersing a load (a pixel writing-in electric current) of a capacitor wiring in a timely manner to effectively reduce the load. A scanning line is formed on a different layer from a gate electrode and the capacitor wiring is arranged so as to be parallel with a signal line. Each pixel is connected to the individually independent capacitor wiring via a dielectric. Therefore, variations in the electric potential of the capacitor wiring caused by a writing-in electric current of a neighboring pixel can be avoided, whereby obtaining satisfactory display images.
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公开(公告)号：US20140327092A1
公开(公告)日：2014-11-06
申请号：US14336153
申请日：2014-07-21
Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
Inventor： Tamae TAKANO , Atsuo ISOBE
IPC: H01L29/786
CPC classification number: H01L29/78606 , H01L27/1214 , H01L27/1266 , H01L27/13 , H01L29/0603 , H01L29/78609 , H01L29/78636
Abstract: The present invention provides a semiconductor device which suppresses a short circuit and a leakage current between a semiconductor film and a gate electrode generated by a break or thin thickness of a gate insulating film in an end portion of a channel region of the semiconductor film, and the manufacturing method of the semiconductor device. Plural thin film transistors which each have semiconductor film provided over a substrate continuously, conductive films provided over the semiconductor film through a gate insulating film, source and drain regions provided in the semiconductor film which are not overlapped with the conductive films, and channel regions provided in the semiconductor film existing under the conductive films and between the source and drain regions. And impurity regions provided in the semiconductor film which is not overlapped with the conductive film and provided adjacent to the source and drain regions. Further, the conductive films are provided over the channel regions and regions of the semiconductor film which are provided adjacent to the channel regions.
Abstract translation: 本发明提供一种半导体器件，其抑制由半导体膜的沟道区域的端部中的栅极绝缘膜的断裂或薄的厚度产生的半导体膜和栅电极之间的短路和漏电流，以及 半导体器件的制造方法。 连续地设置在基板上的半导体膜的多个薄膜晶体管，通过栅极绝缘膜设置在半导体膜上的导电膜，设置在半导体膜中的不与导电膜重叠的源区和漏区，以及设置的沟道区 在存在于导电膜之下以及源极和漏极区之间的半导体膜中。 以及设置在半导体膜中的不与导电膜重叠并且设置在源极和漏极区附近的杂质区。 此外，导电膜设置在与沟道区相邻设置的半导体膜的沟道区域和区域之上。
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公开(公告)号：US20140021476A1
公开(公告)日：2014-01-23
申请号：US14018463
申请日：2013-09-05
Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
Inventor： Hiroshi SHIBATA , Atsuo ISOBE
IPC: H01L29/786
CPC classification number: H01L27/1255 , G02F1/133345 , G02F1/13454 , G02F1/136209 , G02F1/136213 , G02F1/136227 , G02F1/136277 , G02F1/136286 , G02F1/1368 , H01L27/12 , H01L27/1214 , H01L27/124 , H01L27/3244 , H01L27/3248 , H01L27/3262 , H01L27/3265 , H01L27/3276 , H01L29/4908 , H01L29/786 , H01L29/78633
Abstract: To provide a liquid crystal display device having high quality display by obtaining a high aperture ratio while securing a sufficient storage capacitor (Cs), and at the same time, by dispersing a load (a pixel writing-in electric current) of a capacitor wiring in a timely manner to effectively reduce the load. A scanning line is formed on a different layer from a gate electrode and the capacitor wiring is arranged so as to be parallel with a signal line. Each pixel is connected to the individually independent capacitor wiring via a dielectric. Therefore, variations in the electric potential of the capacitor wiring caused by a writing-in electric current of a neighboring pixel can be avoided, whereby obtaining satisfactory display images.
Abstract translation: 为了提供一种通过在确保足够的存储电容器（Cs）的同时获得高开口率而具有高质量显示的液晶显示装置，并且同时通过分散电容器布线的负载（像素写入电流） 及时有效减轻负荷。 扫描线形成在与栅电极不同的层上，电容布线与信号线平行。 每个像素通过电介质连接到单独独立的电容器布线。 因此，可以避免由相邻像素的写入电流引起的电容器布线的电位变化，从而获得令人满意的显示图像。
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公开(公告)号：US20130161606A1
公开(公告)日：2013-06-27
申请号：US13716909
申请日：2012-12-17
Applicant: Semiconductor Energy Laboratory Co., Ltd.
Inventor： Atsuo ISOBE , Hiromichi GODO
IPC: H01L29/786 , H01L29/66
CPC classification number: H01L29/0603 , H01L27/10879 , H01L27/1104 , H01L29/12 , H01L29/66742 , H01L29/66795 , H01L29/785 , H01L29/786 , H01L2029/7858
Abstract: A structure including an oxide semiconductor layer which is provided over an insulating surface and includes a channel formation region and a pair of low-resistance regions between which the channel formation region is positioned, a gate insulating film covering a top surface and a side surface of the oxide semiconductor layer, a gate electrode covering a top surface and a side surface of the channel formation region with the gate insulating film positioned therebetween, and electrodes electrically connected to the low-resistance regions is employed. The electrodes are electrically connected to at least side surfaces of the low-resistance regions, so that contact resistance with the source electrode and the drain electrode is reduced.
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公开(公告)号：US20130092943A1
公开(公告)日：2013-04-18
申请号：US13646086
申请日：2012-10-05
Applicant: Semiconductor Energy Laboratory Co., Ltd.
Inventor： Takehisa HATANO , Sachiaki TEZUKA , Atsuo ISOBE
IPC: H01L21/336 , H01L29/786
CPC classification number: H01L29/66969 , H01L21/0334 , H01L21/467 , H01L27/1156 , H01L27/1207 , H01L27/1225 , H01L29/045 , H01L29/24 , H01L29/42364 , H01L29/42384 , H01L29/78603 , H01L29/7869
Abstract: A semiconductor device which is miniaturized while favorable characteristics thereof are maintained is provided. In addition, the miniaturized semiconductor device is provided with a high yield. The semiconductor device has a structure including an oxide semiconductor film provided over a substrate having an insulating surface; a source electrode layer and a drain electrode layer which are provided in contact with side surfaces of the oxide semiconductor film and have a thickness larger than that of the oxide semiconductor film; a gate insulating film provided over the oxide semiconductor film, the source electrode layer, and the drain electrode layer; and a gate electrode layer provided in a depressed portion formed by a step between a top surface of the oxide semiconductor film and top surfaces of the source electrode layer and the drain electrode layer.
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公开(公告)号：US20220328530A1
公开(公告)日：2022-10-13
申请号：US17845112
申请日：2022-06-21
Applicant: Semiconductor Energy Laboratory Co., Ltd.
Inventor： Wataru UESUGI , Hikaru TAMURA , Atsuo ISOBE
IPC: H01L27/12 , H01L29/786 , H01L49/02 , H01L29/04 , H01L29/78 , H03K19/00 , H03K19/0185 , G11C7/04
Abstract: A retention circuit provided in a logic circuit enables power gating. The retention circuit includes a first terminal, a node, a capacitor, and first to third transistors. The first transistor controls electrical connection between the first terminal and an input terminal of the logic circuit. The second transistor controls electrical connection between an output terminal of the logic circuit and the node. The third transistor controls electrical connection between the node and the input terminal of the logic circuit. A gate of the first transistor is electrically connected to a gate of the second transistor. In a data retention period, the node becomes electrically floating. The voltage of the node is held by the capacitor.
