公开(公告)号：US11646722B2

公开(公告)日：2023-05-09

申请号：US17195713

申请日：2021-03-09

Applicant: Silicon Laboratories Inc.

Inventor： Abdulkerim L. Coban

IPC: H03F3/189 ,  H03K3/037 ,  H03K19/20

CPC classification number: H03K3/037 ,  H03F3/189 ,  H03F2200/294 ,  H03F2200/451 ,  H03K19/20

Abstract: In one embodiment, an apparatus includes a clock generator circuit to receive a first clock signal at a first frequency and output a second clock signal at a second frequency less than the first clock frequency. The clock generator circuit may include: a divider circuit to divide the first clock signal to obtain at least a first divided clock signal and a second divided clock signal; and a gating circuit coupled to the divider circuit, the gating circuit to gate the first clock signal with at least one of the first divided clock signal and the second divided clock signal to output the second clock signal.

公开(公告)号：US10715156B1

公开(公告)日：2020-07-14

申请号：US16369239

申请日：2019-03-29

Applicant: Silicon Laboratories Inc.

Inventor： Abdulkerim L. Coban

IPC: H03L7/099 ,  H03M3/00 ,  H03L7/089 ,  H03F3/189 ,  H03K5/135 ,  H02M3/07

Abstract: A phased-locked loop (PLL) includes a first oscillator supplying a first oscillator signal with a first jitter component and a second oscillator supplying a second oscillator signal with a second jitter component. The second jitter component is higher than the first jitter component. A selector circuit selects either the first oscillator signal or the second oscillator signal as the PLL output signal. The first oscillator signal and the second oscillator signal may have different frequencies with the lower frequency signal having more jitter. The oscillator producing the signal with less jitter utilizes more power. A continuous time delta-sigma modulator analog-to-digital converter (ADC) receives the PLL output signal as an input clock signal. A high gain setting of an amplifier supplying an input signal to the ADC selects a lower jitter signal input clock signal and a lower gain setting selects a higher jitter input clock signal.

公开(公告)号：US20150055021A1

公开(公告)日：2015-02-26

申请号：US14505701

申请日：2014-10-03

Applicant: Silicon Laboratories Inc.

Inventor： Mustafa H. Koroglu ,  Abdulkerim L. Coban

IPC: H04N5/44 ,  H04N5/50 ,  H04N5/455 ,  H04N21/426 ,  H04N21/438

CPC classification number: H04N5/4401 ,  H04N5/455 ,  H04N5/50 ,  H04N21/4263 ,  H04N21/4382

Abstract: An apparatus includes a splitter to receive a radio frequency (RF) signal and to provide the RF signal to multiple channels of a tuner. Each channel may include an amplifier to amplify the RF signal, a mixer to downconvert the amplified RF signal to a second frequency signal using a local oscillator (LO) signal, where each of the channels is configured to receive a different LO signal, a filter to filter the downconverted second frequency signal, and a digitizer to digitize the downconverted second frequency signal. A clock generation circuit has multiple interpolative dividers and a frequency synthesizer to generate a reference clock signal. Each of the interpolative dividers is configured to receive the reference clock signal, generate a corresponding LO signal, and provide the corresponding LO signal to the mixer of at least one of the channels.

Abstract translation: 一种装置包括用于接收射频（RF）信号并将RF信号提供给调谐器的多个信道的分离器。 每个通道可以包括用于放大RF信号的放大器，使用本地振荡器（LO）信号将放大的RF信号下变频到第二频率信号的混频器，其中每个信道被配置为接收不同的LO信号，滤波器 对下变频的第二频率信号进行滤波，以及数字转换器，对下变频的第二频率信号进行数字化。 时钟发生电路具有多个内插分频器和频率合成器，以产生参考时钟信号。 每个内插分频器被配置为接收参考时钟信号，产生相应的LO信号，并将相应的LO信号提供给至少一个信道的混频器。

公开(公告)号：US20140267928A1

公开(公告)日：2014-09-18

申请号：US13799351

申请日：2013-03-13

Applicant: SILICON LABORATORIES INC.

Inventor： Abdulkerim L. Coban ,  Mustafa H. Koroglu

IPC: H04N21/426 ,  H04N21/438

CPC classification number: H04N21/4263 ,  H03J1/0008 ,  H03L7/1974 ,  H04N5/50 ,  H04N21/4383

Abstract: A method includes receiving a request to tune to a first desired television channel of a cable spectrum provided in a radio frequency (RF) signal received in a multi-tuner circuit configured to receive and process the entire cable spectrum, determining a channel of the channels including the first desired television channel, disabling the channels other than the determined channel, and processing the RF signal in the determined channel.

Abstract translation: 一种方法包括接收调谐到在配置成接收和处理整个有线频谱的多调谐器电路中接收的射频（RF）信号中提供的电缆频谱的第一期望电视频道的请求，确定频道的频道 包括第一期望的电视频道，禁止除确定的频道以外的频道，以及处理所确定的频道中的RF信号。

公开(公告)号：US20210175855A1

公开(公告)日：2021-06-10

申请号：US16705868

申请日：2019-12-06

Applicant: Silicon Laboratories Inc.

Inventor： Rangakrishnan Srinivasan ,  Mustafa H. Koroglu ,  Zhongda Wang ,  Francesco Barale ,  Abdulkerim L. Coban ,  John M. Khoury ,  Sriharsha Vasadi ,  Michael S. Johnson ,  Vitor Pereira

IPC: H03F1/26 ,  H03K5/00 ,  H03F3/24 ,  H03F1/30 ,  H03B5/04

Abstract: A transmitter including a frequency synthesizer with a voltage-controlled oscillator that provides an oscillating signal, a programmable delay circuit that delays the oscillating signal to provide a delayed oscillating signal, a power amplifier that is configured to use the delayed oscillating signal for transmitting a signal, and a delay controller that programs the delay circuit with a delay time that reduces interference caused by coupling from the power amplifier to the voltage-controlled oscillator. The delay circuit may be programmed to reduce control voltage change of the voltage-controlled oscillator as a function of delay change, and/or to reduce phase noise degradation at an output of the transmitter as a function of delay change. The delay may be adjusted based on detected operating temperature. A calibration value may be determined at a calibration frequency, in which a frequency offset may be determined based on a selected channel frequency.

公开(公告)号：US10756739B1

公开(公告)日：2020-08-25

申请号：US16369249

申请日：2019-03-29

Applicant: Silicon Laboratories Inc.

Inventor： Abdulkerim L. Coban

IPC: H03L7/093 ,  H02M3/07

Abstract: A unity gain buffer is shared by a charge pump and an active loop filter in a phase-locked loop. The charge pump uses the unity gain buffer to reduce current mismatch in the charge pump and the active loop filter uses the unity gain buffer in a circuit that increases the effective capacitance of the active loop filter.

公开(公告)号：US10033364B1

公开(公告)日：2018-07-24

申请号：US15609160

申请日：2017-05-31

Applicant: SILICON LABORATORIES INC.

Inventor： Abdulkerim L. Coban

IPC: H03D1/00 ,  H04L27/06 ,  H03K5/1532 ,  H03G3/20 ,  H04B1/16

Abstract: A peak detector including an input circuit with five same-sized transistors, in which four of the input transistors are coupled in parallel between a control node and a bias node and receive a corresponding one of two in-phase signals and two quadrature signals. The fifth transistor is coupled between a current node and the bias node and has its control terminal coupled to an output node. A bias circuit establishes a predetermined bias current that flows through the five input transistors. A current mirror mirrors the current through the fifth transistor from the current terminal into the four parallel-coupled input transistors via the control node. An output circuit charges a peak capacitor based on voltage developed at the control terminal of the fifth transistor. The peak detector is low power and compact and detects the actual peak of the input signal with greater accuracy compared to a conventional peak detector.

公开(公告)号：US09219512B2

公开(公告)日：2015-12-22

申请号：US14612346

申请日：2015-02-03

Applicant: Silicon Laboratories Inc.

Inventor： Ramin Khoini-Poorfard ,  Alessandro Piovaccari ,  Aslamali A. Rafi ,  Mustafa H. Koroglu ,  David S. Trager ,  Abdulkerim L. Coban

IPC: H04B1/06 ,  H04N5/50 ,  H04B1/28 ,  H04B1/30 ,  H03H11/04 ,  H04N5/455 ,  H04L27/148

CPC classification number: H04B1/28 ,  H03H11/04 ,  H04B1/30 ,  H04L27/148 ,  H04N5/455 ,  H04N5/50

Abstract: In one form, an integrated receiver includes a tracking bandpass filter, a tunable lowpass filter, and a mixer formed on a single integrated circuit chip. The tracking bandpass filter has an input for receiving a radio frequency (RF) input signal, and an output, and comprises a variable capacitor having a capacitance that varies in response to a bandpass frequency control signal, in parallel with an integrated inductor. The integrated inductor comprises a plurality of windings formed in a plurality of metal layers. The tunable lowpass filter has an input coupled to the output of the tracking bandpass filter, and an output and having a tuning input for receiving a cutoff frequency signal. The mixer has a signal input coupled to the output of the tunable lowpass filter, a local oscillator input for receiving a local oscillator signal, and a signal output for providing a converted RF signal.

Abstract translation: 在一种形式中，集成接收器包括跟踪带通滤波器，可调谐低通滤波器和形成在单个集成电路芯片上的混频器。 跟踪带通滤波器具有用于接收射频（RF）输入信号和输出的输入，并且包括与集成电感器并联的具有响应于带通频率控制信号而变化的电容的可变电容器。 集成电感器包括形成在多个金属层中的多个绕组。 可调谐低通滤波器具有耦合到跟踪带通滤波器的输出的输入端和输出端，并具有用于接收截止频率信号的调谐输入端。 混频器具有耦合到可调谐低通滤波器的输出的信号输入，用于接收本地振荡器信号的本地振荡器输入和用于提供经转换的RF信号的信号输出。

公开(公告)号：US08928820B2

公开(公告)日：2015-01-06

申请号：US13799351

申请日：2013-03-13

Applicant: Silicon Laboratories Inc.

Inventor： Abdulkerim L. Coban ,  Mustafa H. Koroglu

IPC: H04N5/50 ,  H04N5/44 ,  H04N21/426 ,  H04N21/438

CPC classification number: H04N21/4263 ,  H03J1/0008 ,  H03L7/1974 ,  H04N5/50 ,  H04N21/4383

Abstract: A method includes receiving a request to tune to a first desired television channel of a cable spectrum provided in a radio frequency (RF) signal received in a multi-tuner circuit configured to receive and process the entire cable spectrum, determining a channel of the channels including the first desired television channel, disabling the channels other than the determined channel, and processing the RF signal in the determined channel.

Abstract translation: 一种方法包括接收调谐到在被配置为接收和处理整个有线频谱的多调谐器电路中接收的射频（RF）信号中提供的电缆频谱的第一期望电视频道的请求，确定频道的频道 包括第一期望的电视频道，禁止除确定的频道以外的频道，以及处理所确定的频道中的RF信号。

公开(公告)号：US20140267925A1

公开(公告)日：2014-09-18

申请号：US13799384

申请日：2013-03-13

Applicant: SILICON LABORATORIES INC.

Inventor： Mustafa H. Koroglu ,  Abdulkerim L. Coban

IPC: H04N5/44

CPC classification number: H04N5/4401 ,  H04N5/455 ,  H04N5/50 ,  H04N21/4263 ,  H04N21/4382

Abstract: An apparatus includes a splitter to receive a radio frequency (RF) signal and to provide the RF signal to multiple channels of a tuner. Each channel may include an amplifier to amplify the RF signal, a mixer to downconvert the amplified RF signal to a second frequency signal using a local oscillator (LO) signal, where each of the channels is configured to receive a different LO signal, a filter to filter the downconverted second frequency signal, and a digitizer to digitize the downconverted second frequency signal. A clock generation circuit has multiple interpolative dividers and a frequency synthesizer to generate a reference clock signal. Each of the interpolative dividers is configured to receive the reference clock signal, generate a corresponding LO signal, and provide the corresponding LO signal to the mixer of at least one of the channels.

Abstract translation: 一种装置包括用于接收射频（RF）信号并将RF信号提供给调谐器的多个信道的分离器。 每个通道可以包括用于放大RF信号的放大器，使用本地振荡器（LO）信号将放大的RF信号下变频到第二频率信号的混频器，其中每个信道被配置为接收不同的LO信号，滤波器 对下变频的第二频率信号进行滤波，以及数字转换器，对下变频的第二频率信号进行数字化。 时钟发生电路具有多个内插分频器和频率合成器，以产生参考时钟信号。 每个内插分频器被配置为接收参考时钟信号，产生相应的LO信号，并将相应的LO信号提供给至少一个信道的混频器。