公开(公告)号：US11637122B2

公开(公告)日：2023-04-25

申请号：US16925712

申请日：2020-07-10

申请人： SK hynix Inc.

发明人： Kang Sik Choi

IPC分类号： H01L27/115 ,  H01L27/11582 ,  H01L27/11565 ,  H01L27/1157

摘要： A semiconductor device includes a first gate stack structure and a second gate stack structure, which face each other; channel patterns extending in a first direction to penetrate the first gate stack structure and the second gate stack structure; memory patterns extending along outer walls of the channel patterns; and a source contact structure disposed between the first gate stack structure and the second gate stack structure, wherein the source contact structure includes a vertical part extending in the first direction and horizontal protrusion parts protruding toward a sidewall of the first gate stack structure and a sidewall of the second gate stack structure from both sides of the vertical part.

公开(公告)号：US11610915B2

公开(公告)日：2023-03-21

申请号：US17243270

申请日：2021-04-28

申请人： SK hynix Inc.

发明人： Sang Yong Lee ,  Sang Min Kim ,  Jung Ryul Ahn ,  Sang Hyun Oh ,  Seung Bum Cha ,  Kang Sik Choi

IPC分类号： H01L27/11582 ,  H01L25/065 ,  H01L27/06 ,  H01L27/11556

摘要： A semiconductor device includes: a first stack structure; a second stack structure adjacent to the first stack structure in a first direction; a first insulating layer including protrusion parts protruding in a second direction intersecting the first direction and including a concave part defined between the protrusion parts; and a second insulating layer located between the first stack structure and the second stack structure, the second insulating layer inserted into the concave part and the second insulating layer in contact with at least one protrusion part among the protrusion parts.

公开(公告)号：US11437390B2

公开(公告)日：2022-09-06

申请号：US17155834

申请日：2021-01-22

申请人： SK hynix Inc.

发明人： Kang Sik Choi

IPC分类号： H01L27/11556 ,  H01L27/11582 ,  H01L29/06 ,  H01L27/11565 ,  H01L29/08 ,  H01L27/11519 ,  H01L29/78

摘要： Provided herein may be a semiconductor device. The semiconductor device may include a stack. The semiconductor device may include channel layers including channel patterns passing through the stack, dummy channel patterns passing through the stack, and a coupling pattern which may be disposed below the stack and couples the channel patterns with the dummy channel patterns. The semiconductor device may include a bit line which is disposed on the stack and coupled with the channel patterns. The semiconductor device may include a well pick-up line which is disposed on the stack and coupled with the dummy channel patterns.

公开(公告)号：US11239333B2

公开(公告)日：2022-02-01

申请号：US17068396

申请日：2020-10-12

申请人： SK hynix Inc.

发明人： Kang Sik Choi

IPC分类号： H01L29/417 ,  H01L27/11582

摘要： A semiconductor device and a manufacturing method thereof includes a source contact structure, a gate stack structure including a side region adjacent to the source contact structure, and a center region extending from the side region. The semiconductor device further includes a source gate pattern disposed under the side region of the first gate stack structure. The source gate pattern has an inclined surface facing the source contact structure. The semiconductor device also includes a channel pattern penetrating the center region of the gate stack structure, the channel pattern extending toward and contacting the source contact structure.

公开(公告)号：US10930657B2

公开(公告)日：2021-02-23

申请号：US16276442

申请日：2019-02-14

申请人： SK hynix Inc.

发明人： Kang Sik Choi

IPC分类号： H01L27/11556 ,  H01L27/11582 ,  H01L29/06 ,  H01L27/11565 ,  H01L29/08 ,  H01L27/11519 ,  H01L29/78

摘要： Provided herein may be a semiconductor device. The semiconductor device may include a stack. The semiconductor device may include channel layers including channel patterns passing through the stack, dummy channel patterns passing through the stack, and a coupling pattern which may be disposed below the stack and couples the channel patterns with the dummy channel patterns. The semiconductor device may include a bit line which is disposed on the stack and coupled with the channel patterns. The semiconductor device may include a well pick-up line which is disposed on the stack and coupled with the dummy channel patterns.

公开(公告)号：US10263010B2

公开(公告)日：2019-04-16

申请号：US15865669

申请日：2018-01-09

申请人： SK hynix Inc.

发明人： Kang Sik Choi ,  Bong Hoon Lee ,  Seung Cheol Lee

IPC分类号： H01L27/148 ,  H01L21/338 ,  H01L27/11582 ,  H01L29/423 ,  G11C16/04 ,  H01L27/11556 ,  H01L29/66 ,  H01L27/11521 ,  H01L29/788 ,  G11C5/06

摘要： A semiconductor device includes a first semiconductor layer, a second semiconductor layer spaced apart from the first semiconductor layer and disposed on the first semiconductor layer, a gate stack structure disposed on the second semiconductor layer, a third semiconductor layer positioned between the first and second semiconductor layers, and a channel pillar passing through the gate stack structure, the second semiconductor layer and the third semiconductor layer and extending into the first semiconductor layer.

公开(公告)号：US09508428B2

公开(公告)日：2016-11-29

申请号：US15019185

申请日：2016-02-09

申请人： SK hynix Inc.

发明人： Kang Sik Choi

IPC分类号： H01L27/24 ,  G11C13/00 ,  H01L29/66 ,  H01L45/00 ,  H01L27/22

CPC分类号： G11C13/0004 ,  G11C13/004 ,  H01L27/228 ,  H01L27/2454 ,  H01L29/66666 ,  H01L45/04 ,  H01L45/06 ,  H01L45/065 ,  H01L45/1206 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/146 ,  H01L45/147 ,  H01L45/1608 ,  H01L45/1683

摘要： A vertical type semiconductor device and a fabrication method thereof are provided. The vertical type semiconductor device includes a pillar structure having a stacking structure of a conductive layer and a data storage material and formed on a common source region, and a gate electrode formed to surround the data storage material of the pillar structure.

公开(公告)号：US11488962B2

公开(公告)日：2022-11-01

申请号：US17166367

申请日：2021-02-03

申请人： SK hynix Inc.

发明人： Kang Sik Choi

IPC分类号： H01L27/108 ,  G11C5/06

摘要： The disclosure relates to a highly integrated memory device and a method for manufacturing the same. According to the disclosure, a memory device comprises a lower structure, an active layer horizontally oriented parallel to a surface of the lower structure, a bit line connected to a first end of the active layer and vertically oriented from the surface of the lower structure, a capacitor connected to a second end of the active layer, a word line horizontally oriented to be parallel with the active layer along a side surface of the active layer, and a fin channel layer horizontally extending from one side surface of the active layer, wherein the word line includes a protrusion covering the fin channel layer.

公开(公告)号：US11217671B2

公开(公告)日：2022-01-04

申请号：US16812091

申请日：2020-03-06

申请人： SK hynix Inc.

发明人： Kang Sik Choi

IPC分类号： H01L27/11514 ,  H01L29/417 ,  H01L29/423 ,  H01L29/10 ,  H01L27/11582

摘要： A semiconductor device and manufacturing method includes a well structure, a gate stack structure spaced apart from the well structure, the gate stack structure being disposed over the well structure, and a source contact structure facing a sidewall of the gate stack structure. The semiconductor device further includes a channel pattern having pillar parts penetrating the gate stack structure, a first connecting part extending along a bottom surface of the gate stack structure from the pillar parts, and a second connecting part extending from the first connecting part to contact a first surface of the source contact structure facing the well structure.

公开(公告)号：US10950700B2

公开(公告)日：2021-03-16

申请号：US16189563

申请日：2018-11-13

申请人： SK hynix Inc.

发明人： Kang Sik Choi

IPC分类号： H01L29/417 ,  H01L27/11582

摘要： A semiconductor device and a manufacturing method thereof includes a source contact structure, a gate stack structure including a side region adjacent to the source contact structure, and a center region extending from the side region. The semiconductor device further includes a source gate pattern disposed under the side region of the first gate stack structure. The source gate pattern has an inclined surface facing the source contact structure. The semiconductor device also includes a channel pattern penetrating the center region of the gate stack structure, the channel pattern extending toward and contacting the source contact structure.