公开(公告)号：US20160181384A1

公开(公告)日：2016-06-23

申请号：US14581741

申请日：2014-12-23

Applicant: STMICROELECTRONICS, INC. ,  GLOBALFOUNDRIES INC. ,  INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Qing LIU ,  Xiuyu CAI ,  Ruilong XIE ,  Chun-chen YEH

IPC: H01L29/423 ,  H01L29/66 ,  H01L29/40 ,  H01L29/78

CPC classification number: H01L29/4236 ,  H01L29/401 ,  H01L29/42364 ,  H01L29/42384 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66772 ,  H01L29/66795 ,  H01L29/7825 ,  H01L29/78654

Abstract: The present disclosure is directed to a gate structure for a transistor. The gate structure is formed on a substrate and includes a trench. There are sidewalls that line the trench. The sidewalls have a first dimension at a lower end of the trench and a second dimension at an upper end of the trench. The first dimension being larger than the second dimension, such that the sidewalls are tapered from a lower region to an upper region. A high k dielectric liner is formed on the sidewalls and a conductive liner is formed on the high k dielectric liner. A conductive material is in the trench and is adjacent to the conductive liner. The conductive material has a first dimension at the lower end of the trench that is smaller than a second dimension at the upper end of the trench.

Abstract translation: 本公开涉及晶体管的栅极结构。 栅极结构形成在衬底上并且包括沟槽。 有沟槽划线的侧壁。 侧壁在沟槽的下端具有第一尺寸，在沟槽的上端具有第二尺寸。 第一尺寸大于第二尺寸，使得侧壁从下部区域向上部区域逐渐变细。 在侧壁上形成高k电介质衬垫，并且在高k电介质衬垫上形成导电衬垫。 导电材料在沟槽中并且与导电衬垫相邻。 导电材料在沟槽的下端具有小于沟槽上端的第二尺寸的第一尺寸。

公开(公告)号：US20150243660A1

公开(公告)日：2015-08-27

申请号：US14189509

申请日：2014-02-25

Applicant: STMICROELECTRONICS, INC. ,  INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES INC.

Inventor： Qing LIU ,  Xiuyu CAI ,  Chun-chen YEH ,  Ruilong XIE

IPC: H01L27/092 ,  H01L21/285 ,  H01L21/02 ,  H01L29/45 ,  H01L21/8238

Abstract: A method for fabricating a CMOS integrated circuit structure and the CMOS integrated circuit structure. The method includes creating one or more n-type wells, creating one or more p-type wells, creating one or more pFET source-drains embedded in each of the one or more n-type wells, creating one or more nFET source-drains embedded in each of the one or more p-type wells, creating a pFET contact overlaying each of the one or more pFET source-drains, and creating an nFET contact overlaying each of the one or more nFET source-drains. A material of each of the one or more pFET source-drains includes silicon doped with a p-type material; a material of each of the one or more nFET source-drains includes silicon doped with an n-type material; a material of each pFET contact includes nickel silicide; and a material of each nFET contact comprises titanium silicide.

Abstract translation: 一种制造CMOS集成电路结构的方法和CMOS集成电路结构。 该方法包括产生一个或多个n型阱，产生一个或多个p型阱，产生嵌入在一个或多个n型阱中的每一个中的一个或多个pFET源极漏极，产生一个或多个nFET源极漏极 嵌入在所述一个或多个p型阱中的每一个中，产生覆盖所述一个或多个pFET源极漏极中的每一个的pFET触点，以及产生覆盖所述一个或多个nFET源极漏极中的每一个的nFET触点。 一个或多个pFET源极漏极中的每一个的材料包括掺杂有p型材料的硅; 一个或多个nFET源极漏极中的每一个的材料包括掺杂有n型材料的硅; 每个pFET触点的材料包括硅化镍; 并且每个nFET接触的材料包括硅化钛。

公开(公告)号：US20160013206A1

公开(公告)日：2016-01-14

申请号：US14771016

申请日：2013-02-28

Applicant: COMMISSARIAT Á L'ÉNERGIE ATOMIQUE ET AUX ÉNERGIES ALTERNATIVES ,  INTERNATIONAL BUSINESS MACHINES CORPORATION ,  STMICROELECTRONICS, INC.

Inventor： Maud VINET ,  Kangguo CHENG ,  Bruce DORIS ,  Laurent GRENOUILLET ,  Ali KHAKIFIROOZ ,  Yannick LE TIEC ,  Qing LIU

IPC: H01L27/12 ,  H01L21/265 ,  H01L27/092 ,  H01L21/84 ,  H01L21/762 ,  H01L29/06 ,  H01L21/223

CPC classification number: H01L27/1203 ,  H01L21/2236 ,  H01L21/26513 ,  H01L21/76229 ,  H01L21/76237 ,  H01L21/823878 ,  H01L21/823892 ,  H01L21/84 ,  H01L27/0928 ,  H01L29/0649

Abstract: An integrated circuit, including: a UTBOX layer; a first cell, including: FDSOI transistors; a first STI separating the transistors; a first ground plane located beneath one of the transistors and beneath the UTBOX layer; a first well; a second cell, including: FDSOI transistors; a second STI separating the transistors; a second ground plane located beneath one of the transistors and beneath the UTBOX layer; a second well; a third STI separating the cells, reaching the bottom of the first and second wells; a deep well extending continuously beneath the first and second wells, having a portion beneath the third STI whose doping density is at least 50% higher than the doping density of the deep well beneath the first and second STIs.

Abstract translation: 一种集成电路，包括：UTBOX层; 第一个电池，包括：FDSOI晶体管; 分离晶体管的第一STI; 位于一个晶体管下方并位于UTBOX层之下的第一接地平面; 第一口井 第二个电池，包括：FDSOI晶体管; 分离晶体管的第二STI; 位于一个晶体管下方并位于UTBOX层之下的第二接地平面; 第二口井 分离细胞的第三STI，到达第一和第二孔的底部; 连续地在第一和第二阱下方延伸的深阱，具有在第三STI下面的部分，其掺杂密度比第一和第二STI下面的深井的掺杂密度高至少50％。

公开(公告)号：US20160013205A1

公开(公告)日：2016-01-14

申请号：US14771025

申请日：2013-02-28

Applicant: COMMISSARIAT À L'ÉNERGIE ATOMIQUE ET AUX ÉNERGIES ALTERNATIVES ,  INTERNATIONAL BUSINESS MACHINES CORPORATION ,  STMICROELECTRONICS, INC.

Inventor： Maud VINET ,  Kangguo CHENG ,  Bruce DORIS ,  Laurent GRENOUILLET ,  Ali KHAKIFIROOZ ,  Yannick LE TIEC ,  Qing LIU

IPC: H01L27/12 ,  H01L21/84 ,  H01L21/8238 ,  H01L29/06

CPC classification number: H01L27/12 ,  H01L21/762 ,  H01L21/823878 ,  H01L21/823892 ,  H01L21/84 ,  H01L27/1203 ,  H01L27/1207 ,  H01L29/0649 ,  H01L29/0653

Abstract: An integrated circuit, including: a first cell, including: FDSOI transistors; a UTBOX layer lying beneath the transistors; a first well lying beneath the insulator layer and beneath the transistors, the first well having a first type of doping; a first ground plane having a second type of doping, located beneath one of the transistors and between the insulator layer and the first well; a first STI separating the transistors and crossing the insulator layer; a first conductive element forming an electrical connection between the first well and the first ground plane, located under the first STI; a second cell including a second well; a second STI separating the cells, crossing the insulator layer and reaching the bottom of the first and second wells.

Abstract translation: 一种集成电路，包括：第一单元，包括：FDSOI晶体管; 位于晶体管下方的UTBOX层; 第一阱位于绝缘体层之下并位于晶体管下方，第一阱具有第一类掺杂; 具有第二类型掺杂的第一接地平面，位于所述晶体管中的一个之下且在所述绝缘体层和所述第一阱之间; 分离晶体管并与绝缘体层交叉的第一STI; 第一导电元件，其形成位于第一STI之下的第一阱和第一接地平面之间的电连接; 包括第二井的第二池; 分离所述电池的第二STI，穿过所述绝缘体层并到达所述第一和第二阱的底部。

公开(公告)号：US20150349085A1

公开(公告)日：2015-12-03

申请号：US14288766

申请日：2014-05-28

Applicant: STMICROELECTRONICS, INC. ,  GLOBALFOUNDRIES Inc. ,  INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Qing LIU ,  Ruilong XIE ,  Xiuyu CAI ,  Chun-chen YEH

IPC: H01L29/66 ,  H01L29/165 ,  H01L29/78

CPC classification number: H01L29/66795 ,  H01L21/02164 ,  H01L21/02178 ,  H01L21/0228 ,  H01L21/31105 ,  H01L21/823814 ,  H01L21/823821 ,  H01L27/0924 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/165 ,  H01L29/785 ,  H01L29/7851

Abstract: A method for making a semiconductor device includes forming laterally spaced-apart semiconductor fins above a substrate. At least one dielectric layer is formed adjacent an end portion of the semiconductor fins and within the space between adjacent semiconductor fins. A pair of sidewall spacers is formed adjacent outermost semiconductor fins at the end portion of the semiconductor fins. The at least one dielectric layer and end portion of the semiconductor fins between the pair of sidewall spacers are removed. Source/drain regions are formed between the pair of sidewall spacers.

Abstract translation: 制造半导体器件的方法包括在衬底上形成横向间隔开的半导体鳍片。 在半导体鳍片的端部附近和相邻的半导体鳍片之间的空间内形成至少一个电介质层。 在半导体翅片的端部处邻近最外半导体翅片形成一对侧壁间隔物。 去除该对侧壁间隔物之间​​的至少一个电介质层和半导体翅片的端部。 源极/漏极区域形成在该对侧壁间隔物之间​​。

公开(公告)号：US20150333155A1

公开(公告)日：2015-11-19

申请号：US14281021

申请日：2014-05-19

Applicant: STMICROELECTRONICS, INC. ,  GLOBALFOUNDRIES INC ,  INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Qing LIU ,  RUILONG XIE ,  XIUYU CAI ,  CHUN-CHEN YEH ,  KEJIA WANG

IPC: H01L29/66 ,  H01L27/088

CPC classification number: H01L29/66795 ,  H01L21/823431 ,  H01L21/823437 ,  H01L27/0886 ,  H01L29/0653 ,  H01L29/41791 ,  H01L29/66545 ,  H01L29/6656

Abstract: A method for making a semiconductor device may include forming first and second spaced apart semiconductor active regions with an insulating region therebetween, forming at least one sacrificial gate line extending between the first and second spaced apart semiconductor active regions and over the insulating region, and forming sidewall spacers on opposing sides of the at least one sacrificial gate line. The method may further include removing portions of the at least one sacrificial gate line within the sidewall spacers and above the insulating region defining at least one gate line end recess, filling the at least one gate line end recess with a dielectric material, and forming respective replacement gates in place of portions of the at least one sacrificial gate line above the first and second spaced apart semiconductor active regions.

Abstract translation: 制造半导体器件的方法可以包括：形成第一和第二间隔开的半导体有源区域，其间具有绝缘区域，形成在第一和第二间隔开的半导体有源区域之间并在绝缘区域上延伸的至少一个牺牲栅极线，以及形成 在所述至少一个牺牲栅极线的相对侧上的侧壁间隔物。 该方法还可以包括去除侧壁间隔物内的至少一个牺牲栅极线的部分，并且在绝缘区域的上方限定限定至少一个栅极端部凹部的部分，用电介质材料填充至少一个栅极端部凹部，并且形成相应的 替代栅极代替在第一和第二间隔开的半导体有源区之上的至少一个牺牲栅极线的部分。

公开(公告)号：US20170012130A1

公开(公告)日：2017-01-12

申请号：US15273778

申请日：2016-09-23

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES, Inc. ,  STMICROELECTRONICS, INC.

Inventor： Xiuyu CAI ,  Qing LIU ,  Ruilong XIE ,  Chun-Chen YEH

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/417 ,  H01L21/02 ,  H01L21/8234

Abstract: A large area electrical contact for use in integrated circuits features a non-planar, sloped bottom profile. The sloped bottom profile provides a larger electrical contact area, thus reducing the contact resistance, while maintaining a small contact footprint. The sloped bottom profile can be formed by recessing an underlying layer, wherein the bottom profile can be crafted to have a V-shape, U-shape, crescent shape, or other profile shape that includes at least a substantially sloped portion in the vertical direction. In one embodiment, the underlying layer is an epitaxial fin of a FinFET. A method of fabricating the low-resistance electrical contact employs a thin etch stop liner for use as a hard mask. The etch stop liner, e.g., HfO2, prevents erosion of an adjacent gate structure during the formation of the contact.

Abstract translation: 用于集成电路的大面积电接触具有非平面，倾斜的底部轮廓。 倾斜的底部轮廓提供更大的电接触面积，从而降低接触电阻，同时保持小的接触足迹。 倾斜的底部轮廓可以通过凹陷下面的层来形成，其中底部轮廓可以被制造成具有V形，U形，月牙形或其它轮廓形状，其在垂直方向上至少包括基本上倾斜的部分 。 在一个实施例中，下层是FinFET的外延翅片。 制造低电阻电接触的方法采用用作硬掩模的薄蚀刻停止衬垫。 蚀刻停止衬垫，例如HfO 2，防止在形成接触期间相邻栅极结构的侵蚀。

公开(公告)号：US20160190317A1

公开(公告)日：2016-06-30

申请号：US14587655

申请日：2014-12-31

Applicant: STMICROELECTRONICS, INC. ,  GLOBALFOUNDRIES INC. ,  INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Qing LIU ,  Ruilong XIE ,  Chun-chen YEH ,  Xiuyu CAI

IPC: H01L29/78 ,  H01L21/02 ,  H01L29/165 ,  H01L29/40 ,  H01L29/66 ,  H01L29/417

CPC classification number: H01L29/7848 ,  H01L29/165 ,  H01L29/41783 ,  H01L29/6681 ,  H01L29/7842 ,  H01L29/7851

Abstract: A hetero-channel FinFET device provides enhanced switching performance over a FinFET device having a silicon channel, and is easier to integrate into a fabrication process than is a FinFET device having a germanium channel. A FinFET device featuring the heterogeneous Si/SiGe channel includes a fin having a central region made of silicon and sidewall regions made of SiGe. A hetero-channel pFET device in particular has higher carrier mobility and less gate-induced drain leakage current than either a silicon device or a SiGe device. The hetero-channel FinFET permits the SiGe portion of the channel to have a Ge concentration in the range of about 25-40% and permits the fin height to exceed 40 nm while remaining stable.

Abstract translation: 异构沟道FinFET器件在具有硅沟道的FinFET器件上提供增强的开关性能，并且比具有锗通道的FinFET器件更容易集成到制造工艺中。 具有异质Si / SiGe沟道的FinFET器件包括具有由硅构成的中心区域和由SiGe制成的侧壁区域的翅片。 异质沟道pFET器件特别地具有比硅器件或SiGe器件更高的载流子迁移率和更小的栅极引起漏极漏电流。 异质沟道FinFET允许沟道的SiGe部分的Ge浓度在约25-40％的范围内，并且允许翅片高度超过40nm，同时保持稳定。

公开(公告)号：US20160049402A1

公开(公告)日：2016-02-18

申请号：US14461769

申请日：2014-08-18

Applicant: STMICROELECTRONICS, INC. ,  INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES Inc.

Inventor： Qing LIU ,  Chun-chen YEH ,  Ruilong XIE ,  Xiuyu CAl

IPC: H01L27/092 ,  H01L29/161 ,  H01L29/10 ,  H01L29/06 ,  H01L21/02 ,  H01L21/265 ,  H01L21/306 ,  H01L21/308 ,  H01L29/167 ,  H01L21/8238

CPC classification number: H01L27/0924 ,  H01L21/26513 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/823892 ,  H01L29/0653 ,  H01L29/1083 ,  H01L29/161 ,  H01L29/167

Abstract: A method for making a semiconductor device may include forming first and second semiconductor regions laterally adjacent one another and each comprising a first semiconductor material. The method may further include forming an in-situ doped, punch-through stopper layer above the second semiconductor region comprising the first semiconductor material and a first dopant, and forming a semiconductor buffer layer above the punch-through stopper layer, where the punch-through stopper layer includes the first semiconductor material. The method may also include forming a third semiconductor region above the semiconductor buffer layer, where the third semiconductor region includes a second semiconductor material different than the first semiconductor material. In addition, at least one first fin may be formed from the first semiconductor region, and at least one second fin may be formed from the second semiconductor region, the punch-through stopper layer, the semiconductor buffer layer, and the third semiconductor region.

Abstract translation: 制造半导体器件的方法可以包括形成彼此横向相邻的第一和第二半导体区域，并且每个半导体区域包括第一半导体材料。 该方法还可以包括在包括第一半导体材料和第一掺杂剂的第二半导体区域上方形成原位掺杂的穿通阻挡层，并且在穿通阻挡层上方形成半导体缓冲层， 通过阻挡层包括第一半导体材料。 该方法还可以包括在半导体缓冲层之上形成第三半导体区域，其中第三半导体区域包括与第一半导体材料不同的第二半导体材料。 此外，可以从第一半导体区域形成至少一个第一鳍片，并且可以从第二半导体区域，穿通阻挡层，半导体缓冲层和第三半导体区域形成至少一个第二鳍片。

公开(公告)号：US20160190325A1

公开(公告)日：2016-06-30

申请号：US14584161

申请日：2014-12-29

Applicant: STMICROELECTRONICS, INC. ,  INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES Inc.

Inventor： Qing LIU ,  Nicholas LOUBET ,  Chun-chen YEH ,  Ruilong XIE ,  Xiuyu CAI

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/66 ,  H01L29/49 ,  H01L21/768

CPC classification number: H01L29/7856 ,  H01L21/76816 ,  H01L21/76897 ,  H01L29/0657 ,  H01L29/4975 ,  H01L29/6681 ,  H01L2029/7858

Abstract: Tapered source and drain contacts for use in an epitaxial FinFET prevent short circuits and damage to parts of the FinFET during contact processing, thus improving device reliability. The inventive contacts feature tapered sidewalls and a pedestal where electrical contact is made to fins in the source and drain regions. The pedestal also provides greater contact area to the fins, which are augmented by extensions. Raised isolation regions define a valley around the fins. During source/drain contact formation, the valley is lined with a conformal barrier that also covers the fins themselves. The barrier protects underlying local oxide and adjacent isolation regions against gouging while forming the contact. The valley is filled with an amorphous silicon layer that protects the epitaxial fin material from damage during contact formation. A simple tapered structure is used for the gate contact.

Abstract translation: 用于外延FinFET的锥形源极和漏极触点可防止接触处理期间FinFET的短路和损坏，从而提高器件的可靠性。 本发明的触头具有锥形侧壁和与源极和漏极区域中的翅片电接触的基座。 底座还为翅片提供了更大的接触面积，它们通过延伸部分增加。 凸起的隔离区域围绕翅片限定一个谷。 在源极/漏极接触形成期间，谷物衬有也覆盖翅片本身的共形屏障。 当形成接触时，屏障保护底层局部氧化物和相邻隔离区域免受气刨。 该谷填充有非晶硅层，其保护外延翅片材料免于接触形成期间的损坏。 栅极接触使用简单的锥形结构。