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    METHOD OF MANUFACTURING SEMICONDUCTOR DEVICES AND CORRESPONDING DEVICE
    1.
    发明申请
    METHOD OF MANUFACTURING SEMICONDUCTOR DEVICES AND CORRESPONDING DEVICE 有权

    公开(公告)号：US20220059368A1

    公开(公告)日：2022-02-24

    申请号：US17398710

    申请日：2021-08-10

    Applicant: STMicroelectronics S.r.l.

    Inventor： Fulvio Vittorio FONTANA ,  Marco ROVITTO

    IPC: H01L21/48 ,  H01L21/67 ,  H01L23/495

    Abstract: At least one semiconductor chip or die is held within at a chip retaining formation provided in a chip holding device. The chip holding device is then positioned with the at least one semiconductor chip or die arranged facing a chip attachment location in a chip mounting substrate. This positioning produces a cavity between the at least one semiconductor chip or die arranged at the chip retaining formation and the chip attachment location in the chip mounting substrate. A chip attachment material is dispensed into the cavity. Once cured, the chip attachment material attaches the at least one semiconductor chip or die onto the substrate at the chip attachment location in the chip mounting substrate.

    METHOD OF MANUFACTURING SEMICONDUCTOR DEVICES, CORRESPONDING DEVICE AND SYSTEM
    4.
    发明公开
    METHOD OF MANUFACTURING SEMICONDUCTOR DEVICES, CORRESPONDING DEVICE AND SYSTEM 审中-公开

    公开(公告)号：US20230360927A1

    公开(公告)日：2023-11-09

    申请号：US18140375

    申请日：2023-04-27

    Applicant: STMicroelectronics S.r.l.

    Inventor： Fulvio Vittorio FONTANA

    IPC: H01L21/48 ,  H01L21/56 ,  H01L21/033 ,  H01L23/31 ,  H01L23/495

    CPC classification number: H01L21/4828 ,  H01L21/565 ,  H01L21/0335 ,  H01L21/0332 ,  H01L23/3171 ,  H01L23/4951

    Abstract: A semiconductor integrated circuit chip is arranged on a first surface of a substrate that includes electrically conductive lead formations in an array, wherein the electrically conductive lead formations are covered by a masking layer at a second surface opposite the first surface. The semiconductor integrated circuit chip is electrically coupled to electrically conductive lead formations and an insulating encapsulation is molded on the semiconductor integrated circuit chip. The masking layer is then selectively removed, for example, via laser ablation, from one or more of the electrically conductive lead formations. The electrically conductive lead formations that are left uncovered by the masking layer are then removed by an etching process applied to the second surface of the substrate. The selective removal of the unmasked electrically conductive lead formations serves to increase a creepage distance between those conductive lead formations that are left in place.

    SMDS INTEGRATION ON QFN BY 3D STACKED SOLUTION
    5.
    发明申请
    SMDS INTEGRATION ON QFN BY 3D STACKED SOLUTION 有权

    公开(公告)号：US20210249337A1

    公开(公告)日：2021-08-12

    申请号：US17244378

    申请日：2021-04-29

    Applicant: STMICROELECTRONICS S.R.L.

    Inventor： Cristina SOMMA ,  Fulvio Vittorio FONTANA

    IPC: H01L23/495

    Abstract: One or more embodiments are directed to quad flat no-lead (QFN) semiconductor packages, devices, and methods in which one or more electrical components are positioned between a die pad of a QFN leadframe and a semiconductor die. In one embodiment, a device includes a die pad, a lead that is spaced apart from the die pad, and at least one electrical component that has a first contact on the die pad and a second contact on the lead. A semiconductor die is positioned on the at least one electrical component and is spaced apart from the die pad by the at least one electrical component. The device further includes at least one conductive wire, or wire bond, that electrically couples the at least one lead to the semiconductor die.

    METHOD OF MANUFACTURING SEMICONDUCTOR PRODUCTS, SEMICONDUCTOR PRODUCT, DEVICE AND TESTING METHOD
    7.
    发明申请
    METHOD OF MANUFACTURING SEMICONDUCTOR PRODUCTS, SEMICONDUCTOR PRODUCT, DEVICE AND TESTING METHOD 有权

    公开(公告)号：US20210233884A1

    公开(公告)日：2021-07-29

    申请号：US17158781

    申请日：2021-01-26

    Applicant: STMicroelectronics S.r.l.

    Inventor： Fulvio Vittorio FONTANA

    IPC: H01L23/00 ,  H01L21/56 ,  H01L23/31 ,  H01L25/065 ,  G01N21/956

    Abstract: A semiconductor product includes a layer of semiconductor die package molding material embedding a semiconductor die having a front surface and an array of electrically-conductive bodies such as spheres or balls around the semiconductor die. The electrically-conductive bodies have front end portions around the front surface of the semiconductor die and back end portions protruding from the layer of semiconductor die package molding material. Electrically-conductive formations are provided between the front surface of the semiconductor die and front end portions of the electrically-conductive bodies left uncovered by the package molding material. Light-permeable sealing material can be provided at electrically-conductive formations to facilitate inspecting the electrically-conductive formations via visual inspection through the light-permeable sealing material.

    SMDS INTEGRATION ON QFN BY 3D STACKED SOLUTION
    8.
    发明申请
    SMDS INTEGRATION ON QFN BY 3D STACKED SOLUTION 审中-公开

    公开(公告)号：US20190287880A1

    公开(公告)日：2019-09-19

    申请号：US15925420

    申请日：2018-03-19

    Applicant: STMICROELECTRONICS S.R.L.

    Inventor： Cristina SOMMA ,  Fulvio Vittorio FONTANA

    IPC: H01L23/495

    Abstract: One or more embodiments are directed to quad flat no-lead (QFN) semiconductor packages, devices, and methods in which one or more electrical components are positioned between a die pad of a QFN leadframe and a semiconductor die. In one embodiment, a device includes a die pad, a lead that is spaced apart from the die pad, and at least one electrical component that has a first contact on the die pad and a second contact on the lead. A semiconductor die is positioned on the at least one electrical component and is spaced apart from the die pad by the at least one electrical component. The device further includes at least one conductive wire, or wire bond, that electrically couples the at least one lead to the semiconductor die.

    ELECTRONIC DEVICE WITH DIE BEING SUNK IN SUBSTRATE
    9.
    发明申请
    ELECTRONIC DEVICE WITH DIE BEING SUNK IN SUBSTRATE 审中-公开

    公开(公告)号：US20190148282A1

    公开(公告)日：2019-05-16

    申请号：US16245549

    申请日：2019-01-11

    Applicant: STMicroelectronics S.r.l.

    Inventor： Fulvio Vittorio FONTANA ,  Giovanni GRAZIOSI

    IPC: H01L23/498 ,  H01L21/52 ,  H01L23/367 ,  H01L21/48 ,  H01L23/538 ,  H01L23/00

    Abstract: A method for forming an electronic device includes embedding an integrated circuit die in a package including substrate of thermally conductive material with front and back surfaces and a through-hole. The die is sunk in the through-hole. A first insulating material layer covers the die front surface and the package front surface with first windows for accessing die terminals. Package terminals and package track are arranged on the first insulating layer. A second insulating material layer covers the first insulating layer and the package tracks with second windows for accessing the package terminals.

    METHOD OF PRODUCING INTEGRATED CIRCUITS AND CORRESPONDING CIRCUIT
    10.
    发明申请
    METHOD OF PRODUCING INTEGRATED CIRCUITS AND CORRESPONDING CIRCUIT 有权
    生产集成电路和相应电路的方法

    公开(公告)号：US20170040244A1

    公开(公告)日：2017-02-09

    申请号：US15076754

    申请日：2016-03-22

    Applicant: STMICROELECTRONICS S.r.l.

    Inventor： Fulvio Vittorio FONTANA

    IPC: H01L23/495 ,  H01L21/56 ,  H01L23/31 ,  H01L21/48

    CPC classification number: H01L21/4832 ,  H01L21/4825 ,  H01L21/4828 ,  H01L21/565 ,  H01L21/568 ,  H01L23/3107 ,  H01L23/3114 ,  H01L23/49503 ,  H01L23/4952 ,  H01L23/49541 ,  H01L23/49568 ,  H01L23/49582 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/00012 ,  H01L2924/00014

    Abstract: A method may include providing an electrically conductive laminar base member having a die attachment portion and a lead frame portion, producing a distribution of holes opening at a front surface of the base member, attaching an integrated circuit onto the front surface of the base member at the attachment portion, and producing a wire bonding pattern between the integrated circuit and wire bonding locations on the front surface of the base member at the lead frame portion. An electrically insulating package molding compound may be molded onto the front surface of the base member so that the integrated circuit and the wire bonding pattern are embedded in the package molding compound which penetrates into the holes opening at the front surface of the base member. The base member may be selectively etched from its back surface to produce residual portions of the base member at the wire bonding locations.

    Abstract translation: 一种方法可以包括提供具有管芯附接部分和引线框架部分的导电层状基底构件，产生在基底构件的前表面处开口的孔的分布，将集成电路附接到基底构件的前表面上 并且在引线框架部分处在基底构件的前表面上的集成电路和引线接合位置之间产生引线键合图案。 电绝缘包装模塑料可以模制到基底构件的前表面上，使得集成电路和引线接合图案嵌入到穿入基体前表面的孔中的封装模塑料中。 可以从其背面选择性地蚀刻基底构件，以在引线接合位置产生基底构件的残留部分。

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