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    Cryptography method and circuit, corresponding device
    1.
    发明授权
    Cryptography method and circuit, corresponding device 有权

    公开(公告)号：US11456857B2

    公开(公告)日：2022-09-27

    申请号：US16433847

    申请日：2019-06-06

    Applicant: STMicroelectronics S.r.l.

    Inventor： Rosalino Critelli ,  Giuseppe Guarnaccia

    IPC: H04L9/06 ,  G06F13/16 ,  G06F21/60 ,  H04L9/14

    Abstract: A cryptographic method includes providing memory locations for storing encrypted data. The memory locations have respective addresses and are accessible via a communication bus. The method includes receiving over the communication bus access requests to the memory locations, wherein the access requests include burst requests for access to respective sets of the memory locations starting from respective start addresses, and calculating as a function of the start addresses encryption/decryption cryptographic masks based on cryptographic keys. Plain text data is received for encryption and the method includes applying the cryptographic masks to the plain text data to obtain therefrom encrypted data, and including the encrypted data into output data for transmission over the communication bus.

    Decryption method and circuit, corresponding device
    2.
    发明授权
    Decryption method and circuit, corresponding device 有权

    公开(公告)号：US11042655B2

    公开(公告)日：2021-06-22

    申请号：US16296009

    申请日：2019-03-07

    Applicant: STMICROELECTRONICS S.R.L.

    Inventor： Giuseppe Guarnaccia ,  Rosalino Critelli

    IPC: G06F21/00 ,  G06F21/60 ,  G06F21/62 ,  G06F21/85 ,  H04L9/06 ,  G06F21/74

    Abstract: A method for data decryption comprises receiving, over an AXI bus operating in burst mode, data access requests for data units stored in a memory, subdividing the requests received into requests for encrypted data units and requests for non-encrypted data units, forwarding both requests for encrypted data units and requests for non-encrypted data units towards the memory, retrieving the respective sets of data units over the AXI bus, and applying Advanced Encryption Standard, AES, processing to the requests for encrypted data units by calculating decryption masks for the encrypted data units and applying the decryption masks calculated to the encrypted data units retrieved. Subdividing the requests into requests for encrypted data units and requests for non-encrypted data units is performed depending on data start addresses and security information conveyed by the requests.

    METHOD AND APPARATUS FOR SUPPORTING REPROGRAMMING OR RECONFIGURING
    3.
    发明申请
    METHOD AND APPARATUS FOR SUPPORTING REPROGRAMMING OR RECONFIGURING 有权
    支持复制或重新配置的方法和装置

    公开(公告)号：US20150109916A1

    公开(公告)日：2015-04-23

    申请号：US14516300

    申请日：2014-10-16

    Applicant: STMicroelectronics (Grenoble 2) SAS ,  STMicroelectronics S.r.l.

    Inventor： Riccardo Locatelli ,  Michael Soulie ,  Francesco Giotta ,  Raffaele Guarrasi ,  Giuseppe Guarnaccia

    IPC: H04L12/24 ,  H04L12/933 ,  H04L12/851

    CPC classification number: H04L49/109 ,  G06F15/17312 ,  H04L47/24

    Abstract: A method includes setting a first indicator to a first value, which causes an apparatus to stop receiving traffic from a traffic source. At least one register is accessed to read or write at least one new value, and a second indicator is set indicating that accessing of the at least one register has completed. The first indicator is set to a second value. When the first indicator has the second value and the second indicator is set, the apparatus is again allowed to receive traffic from the traffic source.

    Abstract translation: 一种方法包括将第一指示符设置为第一值，这使得设备停止从业务源接收业务。 访问至少一个寄存器以读取或写入至少一个新值，并且设置指示至少一个寄存器的访问已经完成的第二指示符。 第一个指示器被设置为第二个值。 当第一指示符具有第二值并且第二指示符被设置时，再次允许该装置从业务源接收业务。

    CRYPTOGRAPHY METHOD AND CIRCUIT, CORRESPONDING DEVICE
    7.
    发明申请
    CRYPTOGRAPHY METHOD AND CIRCUIT, CORRESPONDING DEVICE 审中-公开

    公开(公告)号：US20190386816A1

    公开(公告)日：2019-12-19

    申请号：US16433847

    申请日：2019-06-06

    Applicant: STMicroelectronics S.r.l.

    Inventor： Rosalino Critelli ,  Giuseppe Guarnaccia

    IPC: H04L9/06 ,  G06F21/60 ,  H04L9/14 ,  G06F13/16

    Abstract: A cryptographic method includes providing memory locations for storing encrypted data. The memory locations have respective addresses and are accessible via a communication bus. The method includes receiving over the communication bus access requests to the memory locations, wherein the access requests include burst requests for access to respective sets of the memory locations starting from respective start addresses, and calculating as a function of the start addresses encryption/decryption cryptographic masks based on cryptographic keys. Plain text data is received for encryption and the method includes applying the cryptographic masks to the plain text data to obtain therefrom encrypted data, and including the encrypted data into output data for transmission over the communication bus.

    Bi-synchronous electronic device with burst indicator and related methods
    8.
    发明授权
    Bi-synchronous electronic device with burst indicator and related methods 有权

    公开(公告)号：US09727306B2

    公开(公告)日：2017-08-08

    申请号：US14508126

    申请日：2014-10-07

    Applicant: STMICROELECTRONICS S.r.l.

    Inventor： Giuseppe Guarnaccia ,  Salvatore Marco Rosselli

    IPC: G06F5/10

    CPC classification number: G06F5/10 ,  G06F2205/102 ,  G06F2205/106

    Abstract: A bi-synchronous electronic device may include a FIFO memory circuit configured to store data, and a first digital circuit coupled to the FIFO memory circuit and configured to operate based upon a first clock signal and a write pointer, write a data burst to the FIFO memory circuit, thereby causing a jump in the write pointer to a new position, and write a burst indicator associated with the new position in the FIFO memory circuit. The bi-synchronous electronic device may include a second digital circuit coupled to the FIFO memory circuit and configured to operate based upon a second clock signal different from the first clock signal, read from the FIFO memory circuit based upon a read pointer, and synchronize the read pointer to the write pointer based upon the burst indicator.

    Bi-synchronous electronic device and FIFO memory circuit with jump candidates and related methods
    9.
    发明授权
    Bi-synchronous electronic device and FIFO memory circuit with jump candidates and related methods 有权
    双同步电子设备和具有跳转候选和FIFO相关方法的FIFO存储器电路

    公开(公告)号：US09311975B1

    公开(公告)日：2016-04-12

    申请号：US14508321

    申请日：2014-10-07

    Applicant: STMICROELECTRONICS S.r.l.

    Inventor： Salvatore Marco Rosselli ,  Giuseppe Guarnaccia ,  Ugo Mari

    IPC: G11C7/22 ,  G06F5/06

    CPC classification number: G11C7/222 ,  G06F5/06 ,  G06F5/10 ,  G06F2205/102

    Abstract: A bi-synchronous electronic device may include a FIFO memory circuit, and a first digital circuit coupled to the FIFO memory circuit and configured to operate based upon a first clock signal, and write to the FIFO memory circuit based upon a write pointer. The bi-synchronous electronic device may include second digital circuit coupled to the FIFO memory circuit and configured to operate based upon a second clock signal different from the first clock signal, and read from the FIFO memory circuit based upon a read pointer. The FIFO memory circuit may be configured to detect a jump in the write pointer to a new position, determine jump candidates for the read pointer from a current position, select a jump candidate, and synchronize the read pointer based upon the selected jump candidate.

    Abstract translation: 双同步电子设备可以包括FIFO存储器电路和耦合到FIFO存储器电路并被配置为基于第一时钟信号进行操作的第一数字电路，并且基于写指针写入FIFO存储器电路。 双同步电子设备可以包括耦合到FIFO存储器电路并被配置为基于与第一时钟信号不同的第二时钟信号进行操作的第二数字电路，并且基于读指针从FIFO存储器电路读取。 FIFO存储器电路可以被配置为检测写指针中的跳转到新位置，从当前位置确定读指针的跳转候选，选择跳转候选，并且基于所选择的跳转候选来同步读指针。

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