公开(公告)号：US20220276972A1

公开(公告)日：2022-09-01

申请号：US17667515

申请日：2022-02-08

Applicant: STMicroelectronics (Rousset) SAS

Inventor： François Tailliet

IPC: G06F13/16 ,  G06F12/02

Abstract: The present description concerns attribution, on a communication over an I2C bus, of a first address to a first device by a second device, wherein the second device sends the first address over the I2C bus and, if the second device receives no acknowledgment data, then the first device records the first address.

公开(公告)号：US11303118B2

公开(公告)日：2022-04-12

申请号：US17165557

申请日：2021-02-02

Applicant: STMicroelectronics (Rousset) SAS

Inventor： François Tailliet

IPC: H02H9/04

Abstract: The present disclosure relates to a device including a rectifying bridge including: a branch connected between first and second nodes; another branch including first and second MOS transistors series-connected between the first and second nodes and having their sources coupled together; a resistor connecting the gate of the first transistor to the second node; another resistor connecting the gate of the second transistor and the first node; and for each transistor, a circuit including first and second terminals respectively connected to the drain and to the gate of the transistor, and being configured to electrically couple its first and second terminals when a voltage between the first terminal of the circuit and the first terminal of the other circuit is greater than a threshold of the circuit.

公开(公告)号：US10732894B2

公开(公告)日：2020-08-04

申请号：US15900481

申请日：2018-02-20

Applicant: STMicroelectronics (Rousset) SAS

Inventor： François Tailliet ,  Marc Battista

IPC: G11C29/00 ,  G06F3/06 ,  G06F11/10 ,  G11C29/52 ,  G06F12/02

Abstract: A method of writing in a memory of the EEPROM type includes, in the presence of a string of new bytes to be written in the memory plane in at least one destination memory word already containing old bytes, a verification for each destination memory word whether or not the old bytes of this destination memory word must all be replaced with new bytes. The method also includes a reading of the old bytes of this destination memory word only if the old bytes must not all be replaced with new bytes.

公开(公告)号：US10727239B2

公开(公告)日：2020-07-28

申请号：US16130593

申请日：2018-09-13

Applicant: STMicroelectronics (Rousset) SAS

Inventor： François Tailliet

IPC: H01L27/11517 ,  H01L29/423 ,  G11C7/18 ,  H01L29/66 ,  G11C16/04 ,  H01L21/28 ,  H01L27/11524 ,  H01L29/788 ,  G11C16/08 ,  G11C16/24

Abstract: An EEPROM memory integrated circuit includes memory cells arranged in a memory plane. Each memory cell includes an access transistor in series with a state transistor. Each access transistor is coupled, via its source region, to the corresponding source line and each state transistor is coupled, via its drain region, to the corresponding bit line. The floating gate of each state transistor rests on a dielectric layer having a first part with a first thickness, and a second part with a second thickness that is less than the first thickness. The second part is located on the source side of the state transistor.

公开(公告)号：US10552365B2

公开(公告)日：2020-02-04

申请号：US15902473

申请日：2018-02-22

Applicant: STMicroelectronics (Rousset) SAS

Inventor： François Tailliet ,  Chama Ameziane El Hassani

IPC: G06F13/42 ,  G06F13/38 ,  G06F13/40 ,  H03K19/00 ,  G06F13/16

Abstract: In some embodiments, a buffer stage device includes a data input for receiving a data signal, a clock input for receiving a clock signal, a data output and a processor that is configured to deliver, to the data output, the data from the data signal in synchronism with clock cycles of the clock signal. The processor includes a first buffer module configured to deliver, to the data output, each datum in synchronism with a first edge of the clock signal and during a first half of a clock cycle, and a second buffer module configured to hold the datum at the data output during the second half of the clock cycle.

公开(公告)号：US10446235B2

公开(公告)日：2019-10-15

申请号：US15984779

申请日：2018-05-21

Applicant: STMicroelectronics (Rousset) SAS

Inventor： François Tailliet

IPC: G11C16/04 ,  G11C16/10 ,  G11C16/14 ,  H01L27/11521 ,  H01L27/11526 ,  H01L29/788

Abstract: A method can be used for writing in a memory location of the electrically-erasable and programmable memory type. The memory location includes a first memory cell with a first transistor having a first gate dielectric underlying a first floating gate and a second memory cell with a second transistor having a second gate dielectric underlying a second floating gate that is connected to the first floating gate. In a first writing phase, an identical tunnel effect is implemented through the first gate dielectric and the second gate dielectric. In a second writing phase, a voltage across the first gate dielectric but not the second gate dielectric is increased.

公开(公告)号：US20190118544A1

公开(公告)日：2019-04-25

申请号：US16220476

申请日：2018-12-14

Applicant: STMicroelectronics (Rousset) SAS

Inventor： François Tailliet ,  Marc Battista ,  Victorien Brecte

IPC: B41J2/175

CPC classification number: B41J2/17556 ,  B41J2/175 ,  B41J2/17523 ,  B41J2/17596 ,  G11C7/067 ,  G11C16/0433 ,  G11C16/24 ,  G11C16/26

Abstract: A read amplifier of a memory device has two current generators, an inverter, and five transistors. The inverter is connected to the second current generator. The first transistor has a gate connected to the read amplifier, a drain connected to the first current generator, and a source connected to a reference ground. The second transistor has a gate connected to the first current generator, a drain connected to a reference voltage, and a source connected to the gate of the first transistor. The third transistor has a drain connected to the first current generator and a source connected to the reference ground. The fourth transistor has a gate connected to the first current generator, a drain connected to the second current generator, and a source connected to the reference ground. The fifth transistor has a drain connected to the second current generator and a source connected to the reference voltage.

公开(公告)号：US20190088665A1

公开(公告)日：2019-03-21

申请号：US16130593

申请日：2018-09-13

Applicant: STMicroelectronics (Rousset) SAS

Inventor： François Tailliet

IPC: H01L27/11517 ,  H01L29/423 ,  H01L29/66 ,  G11C16/04 ,  G11C7/18

Abstract: An EEPROM memory integrated circuit includes memory cells arranged in a memory plane. Each memory cell includes an access transistor in series with a state transistor. Each access transistor is coupled, via its source region, to the corresponding source line and each state transistor is coupled, via its drain region, to the corresponding bit line. The floating gate of each state transistor rests on a dielectric layer having a first part with a first thickness, and a second part with a second thickness that is less than the first thickness. The second part is located on the source side of the state transistor.

公开(公告)号：US10199368B2

公开(公告)日：2019-02-05

申请号：US15436819

申请日：2017-02-19

Applicant: STMicroelectronics (Rousset) SAS

Inventor： François Tailliet

IPC: H01L27/02 ,  H01L29/74 ,  H01L29/866 ,  H02H9/04

Abstract: An integrated circuit includes at least one input-output pad and a terminal intended to be connected to a source of a reference potential and further including a protection structure including a thyristor forward-connected between the pad and the terminal. The thyristor includes a first resistor between its cathode gate and the terminal. At least one Zener diode is disposed between the thyristor and the pad. The anode of the Zener diode is connected to the cathode gate of the thyristor and the cathode of the Zener diode is connected to the pad via at least one second resistor. The junction of the Zener diode is different from the junctions of the PNPN structure of the thyristor.

公开(公告)号：US10049741B2

公开(公告)日：2018-08-14

申请号：US15436829

申请日：2017-02-19

Applicant: STMicroelectronics (Rousset) SAS

Inventor： François Tailliet

IPC: G11C16/04 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11526 ,  H01L27/11556 ,  G11C16/14 ,  G11C16/12 ,  H01L29/423

Abstract: A memory cell includes a source region and a drain region disposed in a semiconductor body. A channel region is disposed in the semiconductor body between the source region and the drain region. A floating gate is disposed between the semiconductor body and the control gate. The floating gate includes a protruding portion that is located over the channel region between the source and drain regions and spaced therefrom. The protruding portion is separated from the channel region by a first insulating layer that is thinner than a second insulating layer that separates remaining portions of the floating gate from the channel region.