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公开(公告)号：US20220239459A1
公开(公告)日：2022-07-28
申请号：US17457354
申请日：2021-12-02
Inventor： Vincent Onde , Diarmuid Emslie , Patrick Valdenaire
IPC: H04L7/00
Abstract: A method for synchronizing a first time domain with a second time domain of a system on chip includes a detection of at least one periodic trigger event generated in the first time domain, the second time domain or in a third time domain; acquisitions, made at the instants of the at least one trigger event, of the current timestamp values representative of the instantaneous states of the time domain(s) other than the trigger time domain; a comparison, made in the third time domain, between differential durations between current timestamp values which are respectively acquired successively; and a synchronization of the second time domain with the first time domain, on the basis of the comparison.
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公开(公告)号：US11086622B2
公开(公告)日：2021-08-10
申请号：US16886245
申请日：2020-05-28
Applicant: STMicroelectronics (Rousset) SAS
Inventor： Vincent Onde
Abstract: Microcode is stored in a program memory and intended to be executed by a central processing unit of a processing unit. The processing unit may include a memory controller associated with each program memory and a hardware peripheral. The method includes, in response to a request to update the microcode, a transmission, to each hardware peripheral, of a global authorization request signal obtained from an elementary authorization request signal generated by each corresponding memory controller, a transmission of a global authorization signal obtained from an elementary authorization signal generated by each hardware peripheral in response to the global authorization request signal and after satisfying a predetermined elementary condition, and an updating of each microcode by the corresponding memory controller only after the global authorization signal is received.
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公开(公告)号：US11079256B2
公开(公告)日：2021-08-03
申请号：US16838337
申请日：2020-04-02
Applicant: STMicroelectronics (Rousset) SAS
Inventor： Vincent Onde
Abstract: A rotary element is equipped with a pattern representing a reflected binary code on at least three bits. A detection circuit is configured to sense the pattern and deliver an incident signal encoded in reflected binary code on at least three bits. The incident signal is converted by a transcoding circuit into an intermediate signal encoded in reflected binary code on two bits. A decoding stage decodes the intermediate signal and outputs at least one clock signal representing the amount of rotation of the rotary element and a direction signal representing the direction of rotation. A processing circuit determines the movement of the rotary element, and has at least one general purpose timer designed to receive the at least one clock signal and direction signal.
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公开(公告)号：US20180095747A1
公开(公告)日：2018-04-05
申请号：US15607615
申请日：2017-05-29
Applicant: STMicroelectronics (Rousset) SAS
Inventor： Vincent Onde
Abstract: Microcode is stored in a program memory and intended to be executed by a central processing unit of a processing unit. The processing unit may include a memory controller associated with each program memory and a hardware peripheral. The method includes, in response to a request to update the microcode, a transmission, to each hardware peripheral, of a global authorization request signal obtained from an elementary authorization request signal generated by each corresponding memory controller, a transmission of a global authorization signal obtained from an elementary authorization signal generated by each hardware peripheral in response to the global authorization request signal and after satisfying a predetermined elementary condition, and an updating of each microcode by the corresponding memory controller only after the global authorization signal is received.
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公开(公告)号：US10298109B2
公开(公告)日：2019-05-21
申请号：US15949690
申请日：2018-04-10
Applicant: STMicroelectronics (Rousset) SAS
Inventor： Jean-Francois Link , Vincent Onde
Abstract: A control signal is applied to a pulse generating circuit configured to generate pulses that are modulated in width. A circuit provides for slope-compensation of the control signal. The circuit includes a digital-to-analog converter that generates a decreasing sawtooth signal. A triggering circuit operates to trigger steps of the sawtooth signal and resetting the sawtooth signal. The sawtooth signal is reset at a cadence of a frequency of the pulses that are modulated in width.
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公开(公告)号：US10648836B2
公开(公告)日：2020-05-12
申请号：US16237938
申请日：2019-01-02
Applicant: STMicroelectronics (Rousset) SAS
Inventor： Vincent Onde
Abstract: A rotary element is equipped with a pattern representing a reflected binary code on at least three bits. A detection circuit is configured to sense the pattern and deliver an incident signal encoded in reflected binary code on at least three bits. The incident signal is converted by a transcoding circuit into an intermediate signal encoded in reflected binary code on two bits. A decoding stage decodes the intermediate signal and outputs at least one clock signal representing the amount of rotation of the rotary element and a direction signal representing the direction of rotation. A processing circuit determines the movement of the rotary element, and has at least one general purpose timer designed to receive the at least one clock signal and direction signal.
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公开(公告)号：US10404263B2
公开(公告)日：2019-09-03
申请号：US15946324
申请日：2018-04-05
Applicant: STMicroelectronics (Rousset) SAS
Inventor： Vincent Onde , Jean-Francois Link
Abstract: A programmable digital-to-analog converter includes an analog circuit that converts a binary word into a value of analog voltage and a digital circuit that supplies the binary word starting from a maximum value decremented by a decrement value.
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公开(公告)号：US10162701B2
公开(公告)日：2018-12-25
申请号：US15888624
申请日：2018-02-05
Applicant: STMicroelectronics (Rousset) SAS
Inventor： Vincent Onde , Dragos Davidescu
IPC: G06F11/10
Abstract: An apparatus having a microcontroller includes a processing unit, an internal communication bus assembly, a volatile memory, a non-volatile memory, a logic error management circuit, and two interface circuits. A first interface circuit couples the processing unit to the volatile memory via the internal communication bus assembly. A second interface circuit couples the processing unit to the non-volatile memory via the internal communication bus assembly. When the microcontroller is operating, the interface circuits are arranged to retrieve and evaluate requested data from their respective memory without intervention from the processing unit. In the event a failure is detected, the logic error management circuit is arranged to assert a stop signal. In some cases, detecting a failure includes comparing a check value stored in memory with a check value calculated from the data retrieved from memory.
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公开(公告)号：US20180157556A1
公开(公告)日：2018-06-07
申请号：US15888624
申请日：2018-02-05
Applicant: STMicroelectronics (Rousset) SAS
Inventor： Vincent Onde , Dragos Davidescu
IPC: G06F11/10
CPC classification number: G06F11/1048
Abstract: An apparatus having a microcontroller includes a processing unit, an internal communication bus assembly, a volatile memory, a non-volatile memory, a logic error management circuit, and two interface circuits. A first interface circuit couples the processing unit to the volatile memory via the internal communication bus assembly. A second interface circuit couples the processing unit to the non-volatile memory via the internal communication bus assembly. When the microcontroller is operating, the interface circuits are arranged to retrieve and evaluate requested data from their respective memory without intervention from the processing unit. In the event a failure is detected, the logic error management circuit is arranged to assert a stop signal. In some cases, detecting a failure includes comparing a check value stored in memory with a check value calculated from the data retrieved from memory.
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10.发明申请
公开(公告)号：US20170350730A1
公开(公告)日：2017-12-07
申请号：US15379329
申请日：2016-12-14
Applicant: STMicroelectronics (Rousset) SAS
Inventor： Vincent Onde
IPC: G01D5/249
CPC classification number: G01D5/249 , G01D4/008 , G01D5/2497 , G01D5/34792 , Y02B90/247 , Y04S20/50
Abstract: A rotary element is equipped with a pattern representing a reflected binary code on at least three bits. A detection circuit is configured to sense the pattern and deliver an incident signal encoded in reflected binary code on at least three bits. The incident signal is converted by a transcoding circuit into an intermediate signal encoded in reflected binary code on two bits. A decoding stage decodes the intermediate signal and outputs at least one clock signal representing the amount of rotation of the rotary element and a direction signal representing the direction of rotation. A processing circuit determines the movement of the rotary element, and has at least one general purpose timer designed to receive the at least one clock signal and direction signal.
