System and method for adaptive run-time reconfiguration for a reconfigurable instruction set co-processor architecture
    1.
    发明授权
    System and method for adaptive run-time reconfiguration for a reconfigurable instruction set co-processor architecture 失效
    用于可重构指令集协处理器架构的自适应运行时重新配置的系统和方法

    公开(公告)号:US08108838B2

    公开(公告)日:2012-01-31

    申请号:US12121542

    申请日:2008-05-15

    摘要: A method for adaptive runtime reconfiguration of a co-processor instruction set, in a computer system with at least a main processor communicatively connected to at least one reconfigurable co-processor, includes the steps of configuring the co-processor to implement an instruction set comprising one or more co-processor instructions, issuing a co-processor instruction to the co-processor, and determining whether the instruction is implemented in the co-processor. For an instruction not implemented in the co-processor instruction set, raising a stall signal to delay the main processor, determining whether there is enough space in the co-processor for the non-implemented instruction, and if there is enough space for said instruction, reconfiguring the instruction set of the co-processor by adding the non-implemented instruction to the co-processor instruction set. The stall signal is cleared and the instruction is executed.

    摘要翻译: 一种在具有通信地连接到至少一个可重配置协处理器的至少一个主处理器的计算机系统中的协处理器指令集的自适应运行时重新配置的方法包括以下步骤:配置协处理器以实现包括 一个或多个协处理器指令,向协处理器发出协处理器指令,以及确定在协处理器中是否实现指令。 对于未在协处理器指令集中实现的指令,提高失速信号以延迟主处理器,确定协处理器中对于未实现指令是否有足够的空间,以及如果存在足够的空间用于所述指令 通过将未实现的指令添加到协处理器指令集来重新配置协处理器的指令集。 停止信号被清除,指令被执行。

    System and Method for Adaptive Run-Time Reconfiguration for a Reconfigurable Instruction Set Co-Processor Architecture
    2.
    发明申请
    System and Method for Adaptive Run-Time Reconfiguration for a Reconfigurable Instruction Set Co-Processor Architecture 失效
    用于可重配置指令集协处理器架构的自适应运行时重配置的系统和方法

    公开(公告)号:US20080215854A1

    公开(公告)日:2008-09-04

    申请号:US12121542

    申请日:2008-05-15

    IPC分类号: G06F9/312

    摘要: A method for adaptive runtime reconfiguration of a co-processor instruction set, in a computer system with at least a main processor communicatively connected to at least one reconfigurable co-processor, includes the steps of configuring the co-processor to implement an instruction set comprising one or more co-processor instructions, issuing a co-processor instruction to the co-processor, and determining whether the instruction is implemented in the co-processor. For an instruction not implemented in the co-processor instruction set, raising a stall signal to delay the main processor, determining whether there is enough space in the co-processor for the non-implemented instruction, and if there is enough space for said instruction, reconfiguring the instruction set of the co-processor by adding the non-implemented instruction to the co-processor instruction set. The stall signal is cleared and the instruction is executed.

    摘要翻译: 一种在具有通信地连接到至少一个可重配置协处理器的至少一个主处理器的计算机系统中的协处理器指令集的自适应运行时重新配置的方法包括以下步骤:配置协处理器以实现包括 一个或多个协处理器指令,向协处理器发出协处理器指令,以及确定在协处理器中是否实现指令。 对于未在协处理器指令集中实现的指令,提高失速信号以延迟主处理器,确定协处理器中对于未实现指令是否有足够的空间,以及如果存在足够的空间用于所述指令 通过将未实现的指令添加到协处理器指令集来重新配置协处理器的指令集。 停止信号被清除,指令被执行。

    System and method for adaptive run-time reconfiguration for a reconfigurable instruction set co-processor architecture
    3.
    发明授权
    System and method for adaptive run-time reconfiguration for a reconfigurable instruction set co-processor architecture 失效
    用于可重构指令集协处理器架构的自适应运行时重新配置的系统和方法

    公开(公告)号:US07523449B2

    公开(公告)日:2009-04-21

    申请号:US11508714

    申请日:2006-08-23

    摘要: A method for adaptive runtime reconfiguration of a co-processor instruction set, in a computer system with at least a main processor communicatively connected to at least one reconfigurable co-processor, includes the steps of configuring the co-processor to implement an instruction set comprising one or more co-processor instructions, issuing a co-processor instruction to the co-processor, and determining whether the instruction is implemented in the co-processor. For an instruction not implemented in the co-processor instruction set, raising a stall signal to delay the main processor, determining whether there is enough space in the co-processor for the non-implemented instruction, and if there is enough space for said instruction, reconfiguring the instruction set of the co-processor by adding the non-implemented instruction to the co-processor instruction set. The stall signal is cleared and the instruction is executed.

    摘要翻译: 一种在具有通信地连接到至少一个可重配置协处理器的至少一个主处理器的计算机系统中的协处理器指令集的自适应运行时重新配置的方法包括以下步骤:配置协处理器以实现包括 一个或多个协处理器指令,向协处理器发出协处理器指令,以及确定在协处理器中是否实现指令。 对于未在协处理器指令集中实现的指令,提高失速信号以延迟主处理器,确定协处理器中对于未实现指令是否有足够的空间,以及如果存在足够的空间用于所述指令 通过将未实现的指令添加到协处理器指令集来重新配置协处理器的指令集。 停止信号被清除,指令被执行。

    System and method for adaptive run-time reconfiguration for a reconfigurable instruction set co-processor architecture
    4.
    发明授权
    System and method for adaptive run-time reconfiguration for a reconfigurable instruction set co-processor architecture 失效
    用于可重构指令集协处理器架构的自适应运行时重新配置的系统和方法

    公开(公告)号:US07167971B2

    公开(公告)日:2007-01-23

    申请号:US10881146

    申请日:2004-06-30

    IPC分类号: G06F9/30 G06F9/00

    摘要: A method for adaptive runtime reconfiguration of a co-processor instruction set, in a computer system with at least a main processor communicatively connected to at least one reconfigurable co-processor, includes the steps of configuring the co-processor to implement an instruction set comprising one or more co-processor instructions, issuing a co-processor instruction to the co-processor, and determining whether the instruction is implemented in the co-processor. For an instruction not implemented in the co-processor instruction set, raising a stall signal to delay the main processor, determining whether there is enough space in the co-processor for the non-implemented instruction, and if there is enough space for said instruction, reconfiguring the instruction set of the co-processor by adding the non-implemented instruction to the co-processor instruction set. The stall signal is cleared and the instruction is executed.

    摘要翻译: 一种在具有通信地连接到至少一个可重配置协处理器的至少一个主处理器的计算机系统中的协处理器指令集的自适应运行时重新配置的方法包括以下步骤:配置协处理器以实现包括 一个或多个协处理器指令,向协处理器发出协处理器指令,以及确定在协处理器中是否实现指令。 对于未在协处理器指令集中实现的指令,提高失速信号以延迟主处理器,确定协处理器中对于未实现指令是否有足够的空间,以及如果存在足够的空间用于所述指令 通过将未实现的指令添加到协处理器指令集来重新配置协处理器的指令集。 停止信号被清除,指令被执行。

    Apparatus and methods employing variable clock gating hysteresis for a communications port
    5.
    发明授权
    Apparatus and methods employing variable clock gating hysteresis for a communications port 有权
    对通信端口采用可变时钟选通滞后的装置和方法

    公开(公告)号:US09285860B2

    公开(公告)日:2016-03-15

    申请号:US12772484

    申请日:2010-05-03

    IPC分类号: G06F1/32 G06F1/04

    摘要: An apparatus includes a communications port configured to communicate over a bus responsive to a clock signal and a clock signal generation circuit configured to generate the clock signal and to vary a gating hysteresis of the clock signal responsive to a control input, such as a communications transaction of the port. The clock signal generation circuit may be configured to vary the gating hysteresis of the clock signal based on an attribute of the transaction, such as an address of the transaction and/or a payload communicated in the transaction.

    摘要翻译: 一种装置包括通信端口,其被配置为响应于时钟信号而通过总线进行通信,以及时钟信号生成电路,其被配置为产生时钟信号,并且响应于诸如通信事务的控制输入而改变时钟信号的门控迟滞 的港口。 时钟信号产生电路可以被配置为基于事务的属性(诸如交易的地址和/或交易中传送的有效载荷)来改变时钟信号的选通滞后。

    Low Latency Clock Gating Scheme for Power Reduction in Bus Interconnects
    6.
    发明申请
    Low Latency Clock Gating Scheme for Power Reduction in Bus Interconnects 审中-公开
    总线互连功率降低的低延迟时钟门控方案

    公开(公告)号:US20130117593A1

    公开(公告)日:2013-05-09

    申请号:US13290250

    申请日:2011-11-07

    IPC分类号: G06F1/32

    摘要: A System-on-a-Chip (SoC) comprising a controller, an activity counter, a reference pattern detection logic, a master pattern detection logic, an arbiter, a comparator, a tracker circuit, a delay cell circuit, and a request mask circuit coupled to a bus. The bus is configured to support master control. The controller is configured to cause components to enter a low power state. The activity counter is configured to monitor activity. The detection logics are configured to operate on an activity based clock or always on clock. The arbiter is configured to select an initiator. The comparator is configured to compare the output of the detection logics. The tracker circuit is configured to track selection of components. The delay cell circuit is configured to store output of components. The request mask circuit is configured to prevent request to arbiter or any arbiter selected request made from a previous clock cycle.

    摘要翻译: 一种片上系统(SoC),包括控制器,活动计数器,参考模式检测逻辑,主模式检测逻辑,仲裁器,比较器,跟踪器电路,延迟单元电路和请求掩码 电路耦合到总线。 总线配置为支持主控制。 控制器被配置为使组件进入低功率状态。 活动计数器配置为监视活动。 检测逻辑被配置为在基于活动的时钟上操作或者始终处于时钟上。 仲裁器被配置为选择启动器。 比较器配置为比较检测逻辑的输出。 跟踪器电路被配置为跟踪组件的选择。 延迟单元电路被配置为存储组件的输出。 请求屏蔽电路被配置为防止对仲裁器的请求或从先前时钟周期进行的任何仲裁器选择的请求。

    Method and apparatus for transmitting memory pre-fetch commands on a bus
    7.
    发明授权
    Method and apparatus for transmitting memory pre-fetch commands on a bus 有权
    一种用于在总线上传送存储器预取命令的方法和装置

    公开(公告)号:US08028143B2

    公开(公告)日:2011-09-27

    申请号:US10929127

    申请日:2004-08-27

    IPC分类号: G06F12/00

    摘要: A processing system and method is disclosed wherein a processor may be configured to predict an address of memory from which data will be needed, transmit to a memory controller a pre-fetch command for the data at the predicted address of the memory, and transmit to the memory controller a read request for the data at the predicted address of the memory if the data is needed.

    摘要翻译: 公开了一种处理系统和方法,其中处理器可以被配置为预测将需要数据的存储器的地址,向存储器控制器发送在存储器的预测地址处的数据的预取命令,并且发送到 如果需要数据,存储器控制器对存储器的预测地址处的数据的读请求。

    Scalable bus structure
    8.
    发明授权
    Scalable bus structure 有权
    可扩展总线结构

    公开(公告)号:US07617343B2

    公开(公告)日:2009-11-10

    申请号:US11070016

    申请日:2005-03-02

    CPC分类号: G06F13/4265

    摘要: A processing system is disclosed with a sending component and a receiving component connected by a bus. The bus may be configured with transmit and receive channels. The transmit channel may have a plurality of sub-channels. The sending component may be configured to broadcast on each of the sub-channels information comprising read and write address locations, read and write control signals, and write data on each of the sub-channels. The receiving component may be configured to store the write data and retrieve read data in response to the information broadcast on any of the sub-channels, and broadcast the retrieved read data on the receive channel to the sending component. The sending component may further be configured to provide to the receiving component independent signaling for each of the sub-channels, the independent signaling being sufficient to allow the receiving component to determine the type of information broadcast on each of the sub-channels.

    摘要翻译: 公开了一种具有通过总线连接的发送部件和接收部件的处理系统。 总线可以配置有发送和接收通道。 发射信道可以具有多个子信道。 发送组件可以被配置为在每个子信道上广播包括读取和写入地址位置,读取和写入控制信号以及每个子信道上的写入数据的信息。 接收组件可以被配置为存储写入数据并且响应于在任何子信道上广播的信息来检索读取数据,并且将接收信道上检索到的读取数据广播到发送组件。 发送组件还可以被配置为向每个子信道的接收组件提供独立的信令,独立信令足以允许接收组件确定在每个子信道上广播的信息的类型。

    Single Bus Command for Transferring Data in a Processing System
    9.
    发明申请
    Single Bus Command for Transferring Data in a Processing System 有权
    用于在处理系统中传输数据的单总线命令

    公开(公告)号:US20070204091A1

    公开(公告)日:2007-08-30

    申请号:US11557119

    申请日:2006-11-07

    IPC分类号: G06F13/36

    CPC分类号: G06F13/28 G06F13/4022

    摘要: A processing system and method for transferring data in a processing system. The processing system includes a bus mastering device, a plurality of slave devices, and a bus interconnect configured to switch the bus mastering device between the slave devices. Each of the slave devices has a plurality of addresses. The bus interconnect includes a DMA controller configured to transfer data from a first one of the addresses to a second one of the addresses in response to a single bus command from the bus mastering device.

    摘要翻译: 一种用于在处理系统中传送数据的处理系统和方法。 处理系统包括总线主控装置,多个从设备和配置成在从设备之间切换总线主控装置的总线互连。 每个从设备具有多个地址。 总线互连包括DMA控制器,其被配置为响应于来自总线主控装置的单个总线命令,将数据从地址的第一个地址传送到第二个地址。

    Method of Associating Groups of Classified Source Addresses with Vibration Patterns
    10.
    发明申请
    Method of Associating Groups of Classified Source Addresses with Vibration Patterns 有权
    将分类源地址组与振动模式相关联的方法

    公开(公告)号:US20070176742A1

    公开(公告)日:2007-08-02

    申请号:US11553600

    申请日:2006-10-27

    IPC分类号: G08B5/22 H04Q7/14

    摘要: In a meeting or group event, people having a portable device, such as a cell phone or pager, may wish to be discretely notified when an important message is received, an urgent call comes in from a selected person or a selected group of people, or to be alerted to an upcoming important event without any audible alert to disturb the meeting or group event. To convey such a notification, a tactile alert is provided by vibrating the portable device according to a unique vibration pattern associated with the received communication. When a communication is received, a group identification (ID) is assigned based on the communication being a member of a classified group of source addresses. The portable device associates the group ID with a unique vibration pattern. To provide the alert, the portable device is vibrated according to the unique vibration pattern.

    摘要翻译: 在会议或小组活动中,具有诸如蜂窝电话或寻呼机的便携式设备的人可能希望在收到重要消息时离散地通知来自所选择的人或所选人群的紧急呼叫, 或者提醒未来的重要事件而没有任何可听见的警报来打扰会议或团体活动。 为了传达这种通知,通过根据与接收的通信相关联的唯一振动模式振动便携式设备来提供触觉警报。 当接收到通信时,基于作为分类的源地址组的成员的通信来分配组标识(ID)。 便携式设备将组ID与唯一的振动模式相关联。 为了提供警报,便携式设备根据独特的振动模式而振动。