-
公开(公告)号：US12161041B2
公开(公告)日：2024-12-03
申请号：US17308671
申请日：2021-05-05
Applicant: Samsung Display Co., LTD.
Inventor： Dae Soo Kim , Sang Gab Kim , Yun Jong Yeo , Ju Hee Lee , Soo Beom Jo , Dae Won Choi
Abstract: An etching device includes a chamber; a stage disposed in the chamber and on which a target substrate is loaded; a gas distribution unit disposed to face the stage in the chamber; a plurality of plasma generation modules disposed above the chamber; a gas supply unit that supplies gas into the chamber; a gas line connecting the gas supply unit and the plurality of plasma generation modules; and a plurality of gas inlet pipes each including an end connected to the plasma generation module and another end connected to the gas distribution unit.
-
公开(公告)号：US12150342B2
公开(公告)日：2024-11-19
申请号：US17467493
申请日：2021-09-07
Applicant: Samsung Display Co., LTD.
Inventor： Dae Won Choi , Dong Won Kim , Sang Gab Kim , Sang Woo Kim , Gyu Jeong Lee , Sung Won Cho
IPC: H10K59/121 , H10K50/844 , H10K59/12 , H10K59/122 , H10K71/00
Abstract: A display device includes a display panel including a main portion, a first bent portion and a second bent portion each extending from the main portion, and a corner portion which connects the first bent portion and the second bent portion to each other and is bendable relative to the main portion. The corner portion which is bendable includes a plurality of protrusion patterns partially disconnected from each other and each bendable relative to the main portion, and each of the plurality of protrusion patterns including a display pixel.
-
公开(公告)号：US11997914B2
公开(公告)日：2024-05-28
申请号：US17255406
申请日：2018-12-21
Applicant: Samsung Display Co., LTD.
Inventor： Hyun Min Cho , Shin Il Choi , Sang Gab Kim , Tae Sung Kim
IPC: H01L29/786 , H10K59/121 , H10K59/124 , H10K71/16 , H10K71/20 , H10K71/00 , H10K102/00
CPC classification number: H10K71/233 , H10K59/1216 , H10K59/124 , H10K71/166 , H10K71/00 , H10K2102/00 , H10K2102/351
Abstract: A method of manufacturing an organic light-emitting display device is provided. The method includes: forming a lower electrode pattern on a substrate, which includes a transistor area and a capacitor area, to correspond to the transistor area and forming a buffer layer on the substrate including the lower electrode pattern; forming a thin-film transistor including an oxide semiconductor layer on the buffer layer; forming an interlayer insulating film on the thin-film transistor; forming a photoresist film pattern including first and second holes, which have different depths, on the interlayer insulating film; and forming a first contact hole, which exposes the lower electrode pattern, and second contact holes, which expose the oxide semiconductor layer, at the same time using the photoresist film pattern.
-
公开(公告)号：US11411066B2
公开(公告)日：2022-08-09
申请号：US17030951
申请日：2020-09-24
Applicant: Samsung Display Co., LTD.
Inventor： Hyun Min Cho , Sang Gab Kim , Tae Sung Kim
Abstract: A display device and a method of the display device are provided. The display device includes a lower metal layer on a substrate, a buffer layer on the lower metal layer, a first semiconductor layer on the buffer layer, a gate insulating layer on the first semiconductor layer, a first gate electrode on the gate insulating layer, an interlayer insulating layer on the first gate electrode, a via layer on the interlayer insulating layer, a pixel electrode on the via layer and electrically connected to the first semiconductor layer, a light emitting layer on the pixel electrode, a common electrode on the light emitting layer, a first contact hole penetrating the buffer layer and the interlayer insulating layer and a second contact hole penetrating the interlayer insulating layer, and a first via hole and a second via hole each penetrating the via layer.
-
公开(公告)号：US11127724B2
公开(公告)日：2021-09-21
申请号：US16691495
申请日：2019-11-21
Applicant: SAMSUNG DISPLAY CO., LTD.
Inventor： Su Bin Bae , Yu Gwang Jeong , Shin Il Choi , Joon Geol Lee , Sang Gab Kim
IPC: H01L21/306 , H01L25/16 , H01L33/20 , H01L33/44 , H01L33/54 , H01L33/62 , H01L25/075 , H01L33/00 , H01L27/12
Abstract: A light emitting diode device includes a thin film transistor substrate having a plurality of light emitting areas, a first diode electrode and a second diode electrode on the thin film transistor substrate, a first passivation pattern between the first diode electrode and the second diode electrode, a plurality of micro light emitting diodes on the first passivation pattern, a first bridge pattern on the micro light emitting diodes and electrically connecting the first diode electrode to the micro light emitting diodes, and a second bridge pattern on the first bridge pattern and electrically connecting the second diode electrode to the micro light emitting diodes, wherein each sidewall of each of the micro light emitting diodes and each sidewall of the first passivation pattern form a same plane.
-
公开(公告)号：US10861978B2
公开(公告)日：2020-12-08
申请号：US16231781
申请日：2018-12-24
Applicant: SAMSUNG DISPLAY CO., LTD.
Inventor： Yong Su Lee , Yoon Ho Khang , Dong Jo Kim , Hyun Jae Na , Sang Ho Park , Se Hwan Yu , Chong Sup Chang , Dae Ho Kim , Jae Neung Kim , Myoung Geun Cha , Sang Gab Kim , Yu-Gwang Jeong
IPC: H01L27/00 , H01L29/00 , H01L29/786 , H01L27/12 , H01L29/66 , H01L29/417 , H01L27/32
Abstract: A thin film transistor according to an exemplary embodiment of the present invention includes an oxide semiconductor. A source electrode and a drain electrode face each other. The source electrode and the drain electrode are positioned at two opposite sides, respectively, of the oxide semiconductor. A low conductive region is positioned between the source electrode or the drain electrode and the oxide semiconductor. An insulating layer is positioned on the oxide semiconductor and the low conductive region. A gate electrode is positioned on the insulating layer. The insulating layer covers the oxide semiconductor and the low conductive region. A carrier concentration of the low conductive region is lower than a carrier concentration of the source electrode or the drain electrode.
-
7.发明申请
公开(公告)号：US20190312147A1
公开(公告)日：2019-10-10
申请号：US16231781
申请日：2018-12-24
Applicant: SAMSUNG DISPLAY CO., LTD.
Inventor： Yong Su Lee , Yoon Ho Khang , Dong Jo Kim , Hyun Jae Na , Sang Ho Park , Se Hwan Yu , Chong Sup Chang , Dae Ho Kim , Jae Neung Kim , Myoung Geun Cha , Sang Gab Kim , Yu-Gwang Jeong
IPC: H01L29/786 , H01L27/12 , H01L29/417 , H01L29/66
Abstract: A thin film transistor according to an exemplary embodiment of the present invention includes an oxide semiconductor. A source electrode and a drain electrode face each other. The source electrode and the drain electrode are positioned at two opposite sides, respectively, of the oxide semiconductor. A low conductive region is positioned between the source electrode or the drain electrode and the oxide semiconductor. An insulating layer is positioned on the oxide semiconductor and the low conductive region. A gate electrode is positioned on the insulating layer. The insulating layer covers the oxide semiconductor and the low conductive region. A carrier concentration of the low conductive region is lower than a carrier concentration of the source electrode or the drain electrode.
-
公开(公告)号：US11320712B2
公开(公告)日：2022-05-03
申请号：US16905306
申请日：2020-06-18
Applicant: Samsung Display Co., LTD.
Inventor： Seon-Il Kim , Sung Won Cho , Sang Gab Kim , Su Bin Bae , Yu-Gwang Jeong , Dae Won Choi
IPC: G02F1/1368 , H01L51/56 , G02F1/1362 , H01L51/52 , H01L27/32
Abstract: A display device includes a thin film transistor on a base substrate and a signal wiring electrically connected to the thin film transistor. The signal wiring includes a main conductive layer including copper, and a capping layer including titanium the capping layer overlapping a portion of an upper surface of the main conductive layer. The signal wiring has a taper angle in a range of about 70° to about 90°. A thickness of the capping layer is in a range of about 100 Å to about 300 Å, and a thickness of the main conductive layer is in a range of about 1,000 Å to about 20,000 Å.
-
公开(公告)号：US10192992B2
公开(公告)日：2019-01-29
申请号：US15704063
申请日：2017-09-14
Applicant: SAMSUNG DISPLAY CO., LTD.
Inventor： Yong Su Lee , Yoon Ho Khang , Dong Jo Kim , Hyun Jae Na , Sang Ho Park , Se Hwan Yu , Chong Sup Chang , Dae Ho Kim , Jae Neung Kim , Myoung Geun Cha , Sang Gab Kim , Yu-Gwang Jeong
IPC: H01L27/00 , H01L29/00 , H01L29/786 , H01L27/12 , H01L29/66 , H01L29/417 , H01L27/32
Abstract: A thin film transistor according to an exemplary embodiment of the present invention includes an oxide semiconductor. A source electrode and a drain electrode face each other. The source electrode and the drain electrode are positioned at two opposite sides, respectively, of the oxide semiconductor. A low conductive region is positioned between the source electrode or the drain electrode and the oxide semiconductor. An insulating layer is positioned on the oxide semiconductor and the low conductive region. A gate electrode is positioned on the insulating layer. The insulating layer covers the oxide semiconductor and the low conductive region. A carrier concentration of the low conductive region is lower than a carrier concentration of the source electrode or the drain electrode.
-
公开(公告)号：US10170502B2
公开(公告)日：2019-01-01
申请号：US15380596
申请日：2016-12-15
Applicant: Samsung Display Co., Ltd.
Inventor： Yu-Gwang Jeong , Hyun Min Cho , Su Bin Bae , Shin Il Choi , Sang Gab Kim
IPC: H01L27/12 , H01L29/417 , H01L21/311 , G02F1/1368 , H01L27/32
Abstract: A transistor array panel is manufactured by a method that reduces or obviates the need for highly selective etching agents or complex processes requiring multiple photomasks to create contact holes. The panel includes: a substrate; a buffer layer positioned on the substrate; a semiconductor layer positioned on the buffer layer; an intermediate insulating layer positioned on the semiconductor layer; and an upper conductive layer positioned on the intermediate insulating layer, wherein the semiconductor layer includes a first contact hole, the intermediate insulating layer includes a second contact hole positioned in an overlapping relationship with the first contact hole, and the upper conductive layer is in contact with a side surface of the semiconductor layer in the first contact hole.
