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1.发明授权公开(公告)号：US11462574B2
公开(公告)日：2022-10-04
申请号：US16896146
申请日：2020-06-08
Applicant: SAMSUNG DISPLAY CO., LTD.
Inventor： Sungwon Cho , Yu-Gwang Jeong , Daewon Choi , Seon-Il Kim , Subin Bae , Yun Jong Yeo
IPC: H01L27/14 , H01L27/12 , H01L29/786
Abstract: A display substrate includes a substrate, a first gate electrode on the substrate, a first gate insulating layer on the first gate electrode, an active layer on the first gate insulating layer, a second gate insulating layer on the active layer, a second gate electrode on the second gate insulating layer, an interlayer insulating layer on the second gate electrode, a first electrode on the interlayer insulating layer to contact a top surface, a side wall, and a bottom surface of the active layer via a first contact hole through the interlayer insulating layer, the second gate insulating layer, the active layer, and a portion of the first gate insulating layer, and a second electrode on the interlayer insulating layer to contact the first gate electrode via a second contact hole through the interlayer insulating layer, the second gate insulating layer, and the first gate insulating layer.
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公开(公告)号：US11211441B2
公开(公告)日：2021-12-28
申请号：US16199226
申请日：2018-11-26
Applicant: Samsung Display Co., LTD.
Inventor： Yu-Gwang Jeong , Subin Bae , Joongeol Lee , Sanggab Kim
Abstract: An OLED device includes a substrate, a first active layer, a first gate electrode, a second gate electrode, first source and first drain electrodes, a first high dielectric constant (high-k) insulation structure, and a light emitting structure. The substrate has a first region and a second region. The first active layer is disposed in the first region on the substrate. The first gate electrode is disposed on the first active layer, and has a first thickness. The second gate electrode is disposed on the first gate electrode. The first source electrode and first drain electrode are disposed on the second gate electrode, and constitutes a first semiconductor element together with the first active layer and the first gate electrode. The first high-k insulation structure is disposed between the first gate electrode and the second gate electrode, and is spaced apart from the first source electrode and first drain electrode.
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公开(公告)号：US10861978B2
公开(公告)日：2020-12-08
申请号：US16231781
申请日：2018-12-24
Applicant: SAMSUNG DISPLAY CO., LTD.
Inventor： Yong Su Lee , Yoon Ho Khang , Dong Jo Kim , Hyun Jae Na , Sang Ho Park , Se Hwan Yu , Chong Sup Chang , Dae Ho Kim , Jae Neung Kim , Myoung Geun Cha , Sang Gab Kim , Yu-Gwang Jeong
IPC: H01L27/00 , H01L29/00 , H01L29/786 , H01L27/12 , H01L29/66 , H01L29/417 , H01L27/32
Abstract: A thin film transistor according to an exemplary embodiment of the present invention includes an oxide semiconductor. A source electrode and a drain electrode face each other. The source electrode and the drain electrode are positioned at two opposite sides, respectively, of the oxide semiconductor. A low conductive region is positioned between the source electrode or the drain electrode and the oxide semiconductor. An insulating layer is positioned on the oxide semiconductor and the low conductive region. A gate electrode is positioned on the insulating layer. The insulating layer covers the oxide semiconductor and the low conductive region. A carrier concentration of the low conductive region is lower than a carrier concentration of the source electrode or the drain electrode.
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公开(公告)号：US10720501B2
公开(公告)日：2020-07-21
申请号：US16563948
申请日：2019-09-09
Applicant: Samsung Display Co., Ltd.
Inventor： Yu-Gwang Jeong , Shin-Il Choi , Su-Bin Bae , Sung-Hoon Yang
IPC: H01L29/417 , H01L27/12 , H01L29/45 , H01L29/66 , H01L23/532
Abstract: According to an exemplary embodiment, a display substrate includes a gate metal pattern comprising a gate electrode, an active pattern disposed on the gate pattern and a source metal pattern disposed on the active pattern. The source metal pattern includes a first lower pattern disposed on the active pattern, a second lower pattern disposed on the first lower pattern, a low-resistance metal pattern disposed on the second lower pattern, and an upper pattern disposed on the low-resistance metal pattern. The first lower pattern, the second lower pattern, and the upper pattern each include a material that is the same.
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5.发明申请
公开(公告)号：US20190312147A1
公开(公告)日：2019-10-10
申请号：US16231781
申请日：2018-12-24
Applicant: SAMSUNG DISPLAY CO., LTD.
Inventor： Yong Su Lee , Yoon Ho Khang , Dong Jo Kim , Hyun Jae Na , Sang Ho Park , Se Hwan Yu , Chong Sup Chang , Dae Ho Kim , Jae Neung Kim , Myoung Geun Cha , Sang Gab Kim , Yu-Gwang Jeong
IPC: H01L29/786 , H01L27/12 , H01L29/417 , H01L29/66
Abstract: A thin film transistor according to an exemplary embodiment of the present invention includes an oxide semiconductor. A source electrode and a drain electrode face each other. The source electrode and the drain electrode are positioned at two opposite sides, respectively, of the oxide semiconductor. A low conductive region is positioned between the source electrode or the drain electrode and the oxide semiconductor. An insulating layer is positioned on the oxide semiconductor and the low conductive region. A gate electrode is positioned on the insulating layer. The insulating layer covers the oxide semiconductor and the low conductive region. A carrier concentration of the low conductive region is lower than a carrier concentration of the source electrode or the drain electrode.
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6.发明授权
公开(公告)号：US09978777B2
公开(公告)日：2018-05-22
申请号：US15392888
申请日：2016-12-28
Applicant: Samsung Display Co., Ltd.
Inventor： Tae An Seo , Su Bin Bae , Yu-Gwang Jeong , Hyun Min Cho , Shin Il Choi , Jin Hwan Choi
IPC: H01L27/12 , H01L29/66 , H01L29/786
CPC classification number: H01L27/1225 , H01L27/124 , H01L27/1288 , H01L29/66969 , H01L29/7869
Abstract: A TFT array panel of a display device includes a first substrate, a first electrode disposed on the first substrate, a first insulating layer including a first hole, the first insulating layer disposed on the first electrode, a second insulating layer disposed on the first insulating layer and including a second hole corresponding to the first hole, and a capping layer including a first inner portion, the capping layer disposed on an inner lateral surface forming the second hole, where an end portion of the first inner portion disposed in the second hole is separated from the first electrode.
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公开(公告)号：US09443881B2
公开(公告)日：2016-09-13
申请号：US14518278
申请日：2014-10-20
Applicant: SAMSUNG DISPLAY CO., LTD.
Inventor： Jean-Ho Song , Shin-Il Choi , Sun-Young Hong , Shi-Yul Kim , Ki-Yeup Lee , Jae-Hyoung Youn , Sung-Ryul Kim , O-Sung Seo , Yang-Ho Bae , Jong-Hyun Choung , Dong-Ju Yang , Bong-Kyun Kim , Hwa-Yeul Oh , Pil-Soon Hong , Byeong-Beom Kim , Je-Hyeong Park , Yu-Gwang Jeong , Jong-In Kim , Nam-Seok Suh
IPC: H01L29/04 , H01L27/12 , H01L29/423 , H01L29/45 , H01L29/786
CPC classification number: H01L27/124 , H01L27/12 , H01L27/1214 , H01L27/1288 , H01L29/42368 , H01L29/458 , H01L29/78669
Abstract: A thin film transistor array panel includes a gate line, a gate insulating layer that covers the gate line, a semiconductor layer that is disposed on the gate insulating layer, a data line and drain electrode that are disposed on the semiconductor layer, a passivation layer that covers the data line and drain electrode and has a contact hole that exposes a portion of the drain electrode, and a pixel electrode that is electrically connected to the drain electrode through the contact hole. The data line and drain electrode each have a double layer that includes a lower layer of titanium and an upper layer of copper, and the lower layer is wider than the upper layer, and the lower layer has a region that is exposed. The gate insulating layer may have a step shape.
Abstract translation: 薄膜晶体管阵列面板包括栅极线，覆盖栅极线的栅极绝缘层，设置在栅极绝缘层上的半导体层，设置在半导体层上的数据线和漏极，钝化层 覆盖数据线和漏电极，并且具有露出漏电极的一部分的接触孔，以及通过接触孔与漏电极电连接的像素电极。 数据线和漏极各自具有包括钛的下层和铜的上层的双层，下层比上层宽，下层具有暴露的区域。 栅极绝缘层可以具有台阶形状。
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公开(公告)号：US09236401B2
公开(公告)日：2016-01-12
申请号：US14195051
申请日：2014-03-03
Applicant: Samsung Display Co., Ltd.
Inventor： Jae-Neung Kim , Yu-Gwang Jeong , Sang-Gab Kim , Su-Bin Bae , Shin-Il Choi
IPC: G02F1/1343 , G02F1/1362 , H01L27/12
CPC classification number: H01L27/1225 , G02F1/134309 , G02F1/136213 , G02F2201/50 , H01L27/1248 , H01L27/1255 , H01L27/1259
Abstract: A display apparatus includes: a substrate defining transistor and wiring areas; a thin film transistor in the transistor area and including a gate electrode, an active layer, and source and drain electrodes; an etch prevention layer in the transistor area, absent in the wiring area and covering the active layer, and first and second contact holes defined in the etch prevention layer and through which the active layer is electrically coupled to the source and drain electrodes; a first wiring layer in the wiring area; a first insulating layer which covers the gate electrode and the first wiring layer, and a third contact hole defined in the first insulating layer in the wiring area and exposing the first wiring layer; and a second wiring layer on the first insulating layer and in the wiring area, and electrically coupled to the first wiring layer via the third contact hole.
Abstract translation: 显示装置包括：限定晶体管和布线区域的基板; 晶体管区域中的薄膜晶体管，并且包括栅电极，有源层以及源极和漏极; 晶体管区域中的防蚀层，在布线区域中不存在并覆盖有源层，以及限定在防蚀层中的第一和第二接触孔，有源层电耦合到源电极和漏电极; 布线区域中的第一布线层; 覆盖所述栅电极和所述第一布线层的第一绝缘层和限定在所述布线区域中的所述第一绝缘层中的第三接触孔，并暴露所述第一布线层; 以及在所述第一绝缘层和所述布线区域中的第二布线层，并且经由所述第三接触孔电耦合到所述第一布线层。
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公开(公告)号：US09064750B2
公开(公告)日：2015-06-23
申请号：US13869697
申请日：2013-04-24
Applicant: Samsung Display Co., LTD.
Inventor： Yu-Gwang Jeong , Ji-Young Park , Shin-Il Choi , Sang-Gab Kim
IPC: H01L29/786 , H01L27/13 , G02F1/1345 , H01L27/12 , G02F1/1337 , H01L33/02
CPC classification number: H01L27/124 , G02F1/133707 , H01L27/1248 , H01L27/1288
Abstract: A method of manufacturing a display substrate includes forming a gate insulation layer on the base substrate on which a gate metal pattern, forming a data metal pattern on the gate insulation layer, sequentially forming a insulation layer and an organic layer on the base substrate on which the data metal pattern is formed, partially exposing the organic layer, developing the organic layer to partially remove the organic layer on the data metal pattern and to expose at least a portion of the protecting layer on the gate metal pattern, forming a common electrode on the organic layer, forming a pixel electrode on the on the organic layer, and forming an insulation layer between the pixel electrode and the common electrode. An etching degree of a data metal may be controlled by controlling a thickness of a remained organic layer to reduce a damage of the data metal.
Abstract translation: 一种制造显示基板的方法包括在基底基板上形成栅极绝缘层，栅基金属图案在栅绝缘层上形成数据金属图案，在基底基板上依次形成绝缘层和有机层， 形成数据金属图案，部分地暴露有机层，显影有机层以部分地去除数据金属图案上的有机层，并暴露栅极金属图案上的保护层的至少一部分，形成公共电极 有机层，在有机层上形成像素电极，在像素电极和公共电极之间形成绝缘层。 可以通过控制剩余的有机层的厚度来减少数据金属的损伤来控制数据金属的蚀刻程度。
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公开(公告)号：US20150053984A1
公开(公告)日：2015-02-26
申请号：US14518278
申请日：2014-10-20
Applicant: SAMSUNG DISPLAY CO., LTD.
Inventor： JEAN-HO SONG , Shin-Il Choi , Sun-Young Hong , Shi-Yul Kim , Ki-Yeup Lee , Jae-Hyoung Youn , Sung-Ryul Kim , O-Sung Seo , Yang-Ho Bae , Jong-Hyun Choung , Dong-Ju Yang , Bong-Kyun Kim , Hwa-Yeul Oh , Pil-Soon Hong , Byeong-Beom Kim , Je-Hyeong Park , Yu-Gwang Jeong , Jong-In Kim , Nam-Seok Suh
IPC: H01L27/12 , H01L29/45 , H01L29/423 , H01L29/786
CPC classification number: H01L27/124 , H01L27/12 , H01L27/1214 , H01L27/1288 , H01L29/42368 , H01L29/458 , H01L29/78669
Abstract: A thin film transistor array panel includes a gate line, a gate insulating layer that covers the gate line, a semiconductor layer that is disposed on the gate insulating layer, a data line and drain electrode that are disposed on the semiconductor layer, a passivation layer that covers the data line and drain electrode and has a contact hole that exposes a portion of the drain electrode, and a pixel electrode that is electrically connected to the drain electrode through the contact hole. The data line and drain electrode each have a double layer that includes a lower layer of titanium and an upper layer of copper, and the lower layer is wider than the upper layer, and the lower layer has a region that is exposed. The gate insulating layer may have a step shape.
Abstract translation: 薄膜晶体管阵列面板包括栅极线，覆盖栅极线的栅极绝缘层，设置在栅极绝缘层上的半导体层，设置在半导体层上的数据线和漏极，钝化层 覆盖数据线和漏电极，并且具有露出漏电极的一部分的接触孔，以及通过接触孔与漏电极电连接的像素电极。 数据线和漏极各自具有包括钛的下层和铜的上层的双层，下层比上层宽，下层具有暴露的区域。 栅极绝缘层可以具有台阶形状。
