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公开(公告)号：US11086745B2
公开(公告)日：2021-08-10
申请号：US16573101
申请日：2019-09-17
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Kui-Yon Mun , Jae-Yong Jeong , Sung-Kyu Park , Beomkyu Shin , Young-Seok Hong
Abstract: A memory system includes a memory device, a first controller, and a second controller. The first controller is configured to output a control signal for the memory device and data to be stored in the memory device based on a signal received from a host. The second controller includes a non-volatile memory configured to store the data. The second controller is configured to receive the control signal and the data from the first controller, and control the memory device based on the control signal.
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公开(公告)号：US20200241989A1
公开(公告)日：2020-07-30
申请号：US16573101
申请日：2019-09-17
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Kui-Yon Mun , Jae-Yong Jeong , Sung-Kyu Park , Beomkyu Shin , Young-Seok Hong
Abstract: A memory system includes a memory device, a first controller, and a second controller. The first controller is configured to output a control signal for the memory device and data to be stored in the memory device based on a signal received from a host. The second controller includes a non-volatile memory configured to store the data. The second controller is configured to receive the control signal and the data from the first controller, and control the memory device based on the control signal.
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公开(公告)号：US10573386B2
公开(公告)日：2020-02-25
申请号：US16035958
申请日：2018-07-16
Applicant: Samsung Electronics Co., Ltd.
Inventor： Wan-Dong Kim , Tae-Hyun Kim , Sang-Wan Nam , Sang-Soo Park , Jae-Yong Jeong
IPC: G11C16/04 , G11C16/08 , G11C16/28 , G11C16/10 , G11C16/26 , G11C16/34 , G11C11/56 , G11C16/32 , G11C5/06
Abstract: To operate a memory device including a plurality of NAND strings, an unselected NAND string among a plurality of NAND strings is floated when a voltage of a selected word line is increased such that a channel voltage of the unselected NAND string is boosted. The channel voltage of the unselected NAND string may be discharged when the voltage of the selected word line is decreased. The load when the voltage of the selected word line increases may be reduced by floating the unselected NAND string to boost the channel voltage of the unselected NAND string together with the increase of the voltage of the selected word line. The load when the voltage of the selected word line is decreased may be reduced by discharging the boosted channel voltage of the unselected NAND string when the voltage of the selected word line is decreased. Through such reduction of the load of the selected word line, a voltage setup time may be reduced and an operation speed of the memory device may be enhanced.
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公开(公告)号：US09147483B2
公开(公告)日：2015-09-29
申请号：US14068122
申请日：2013-10-31
Applicant: Samsung Electronics Co., Ltd.
Inventor： Hyun-Jun Yoon , Jae-Yong Jeong , Myoung-Hoon Choi , Bo-Geun Kim , Ki-Tae Park
CPC classification number: G11C16/26 , G06F11/1048 , G11C11/5642 , G11C16/3422 , G11C2029/0411 , G11C2211/5641
Abstract: A memory device useable with a memory system includes a voltage generator to a plurality of first candidate voltages and a plurality of second candidate voltages, and an X decoder to sequentially apply each of the plurality of first candidate voltages and each of the plurality of second candidate voltages to one or more cells of a memory cell array, and then to apply one of the plurality of first candidate voltages and one of the plurality of second candidate voltages as a first read voltage and a second voltage, respectively, to read data from the cells of the memory cell array according to a characteristic of the cells of the memory cell array.
Abstract translation: 可与存储器系统一起使用的存储装置包括电压发生器到多个第一候选电压和多个第二候选电压，以及X解码器，以顺序地施加多个第一候选电压中的每一个，并且多个第二候选 电压到存储单元阵列的一个或多个单元，然后分别施加多个第一候选电压和多个第二候选电压中的一个作为第一读取电压和第二电压以从 根据存储单元阵列的单元的特性，存储单元阵列的单元。
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公开(公告)号：US11657858B2
公开(公告)日：2023-05-23
申请号：US17338097
申请日：2021-06-03
Applicant: Samsung Electronics Co., Ltd.
Inventor： Hyun-Jin Kim , Chung-Ho Yu , Yong-Kyu Lee , Jae-Yong Jeong
IPC: G11C7/10
CPC classification number: G11C7/1039 , G11C7/1012 , G11C7/1057 , G11C7/1084
Abstract: A nonvolatile memory device may include a plurality of memory planes and a plurality of plane-dedicated pad sets. The plurality of memory planes may include a plurality of memory cell arrays including nonvolatile memory cells and a plurality of page buffer circuits. Each of the plurality of page buffer circuits may be connected to ones of the nonvolatile memory cells included in each of the plurality of memory cell arrays through bitlines. A plurality of plane-dedicated pad sets may be connected to the plurality of page buffer circuits through a plurality of data paths respectively such that each of the plurality plane-dedicated pad sets is dedicatedly connected to each of the plurality of page buffer circuits. A bandwidth of a data transfer may be increased by reducing a data transfer delay and supporting a parallel data transfer, and power consumption may be decreased by removing data multiplexing and/or signal routing.
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公开(公告)号：US20210295884A1
公开(公告)日：2021-09-23
申请号：US17338097
申请日：2021-06-03
Applicant: Samsung Electronics Co., Ltd.
Inventor： HYUN-JIN KIM , Chung-Ho Yu , Yong-Kyu Lee , Jae-Yong Jeong
IPC: G11C7/10
Abstract: A nonvolatile memory device may include a plurality of memory planes and a plurality of plane-dedicated pad sets. The plurality of memory planes may include a plurality of memory cell arrays including nonvolatile memory cells and a plurality of page buffer circuits. Each of the plurality of page buffer circuits may be connected to ones of the nonvolatile memory cells included in each of the plurality of memory cell arrays through bitlines. A plurality of plane-dedicated pad sets may be connected to the plurality of page buffer circuits through a plurality of data paths respectively such that each of the plurality plane-dedicated pad sets is dedicatedly connected to each of the plurality of page buffer circuits. A bandwidth of a data transfer may be increased by reducing a data transfer delay and supporting a parallel data transfer, and power consumption may be decreased by removing data multiplexing and/or signal routing.
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公开(公告)号：US11600539B2
公开(公告)日：2023-03-07
申请号：US17356152
申请日：2021-06-23
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Min-Jae Lee , Sang-Lok Kim , Byung-Hoon Jeong , Tae-Sung Lee , Jeong-Don Ihm , Jae-Yong Jeong , Young-Don Choi
IPC: G01R31/64 , H01L21/66 , H01L23/528 , G01R31/3187
Abstract: A semiconductor device includes a semiconductor die, a defect detection structure and an input-output circuit. The semiconductor die includes a central region and a peripheral region surrounding the central region. The peripheral region includes a left-bottom corner region, a left-upper corner region, a right-upper corner region and a right-bottom corner region. The defect detection structure is formed in the peripheral region. The defect detection structure includes a first conduction loop in the left-bottom corner region, a second conduction loop in the right-bottom corner region, a third conduction loop in the left-bottom corner region and the left-upper corner region and a fourth conduction loop in the right-bottom corner region and the right-upper corner region. The input-output circuit is electrically connected to end nodes of the first conduction loop, the second conduction loop, the third conduction loop and the fourth conduction loop.
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公开(公告)号：US11062966B2
公开(公告)日：2021-07-13
申请号：US16357674
申请日：2019-03-19
Applicant: Samsung Electronics Co., Ltd.
Inventor： Min-Jae Lee , Sang-Lok Kim , Byung-Hoon Jeong , Tae-Sung Lee , Jeong-Don Ihm , Jae-Yong Jeong , Young-Don Choi
IPC: H01L21/26 , H01L21/66 , H01L23/528 , G01R31/3187
Abstract: A semiconductor device includes a semiconductor die, a defect detection structure and an input-output circuit. The semiconductor die includes a central region and a peripheral region surrounding the central region. The peripheral region includes a left-bottom corner region, a left-upper corner region, a right-upper corner region and a right-bottom corner region. The defect detection structure is formed in the peripheral region. The defect detection structure includes a first conduction loop in the left-bottom corner region, a second conduction loop in the right-bottom corner region, a third conduction loop in the left-bottom corner region and the left-upper corner region and a fourth conduction loop in the right-bottom corner region and the right-upper corner region. The input-output circuit is electrically connected to end nodes of the first conduction loop, the second conduction loop, the third conduction loop and the fourth conduction loop.
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公开(公告)号：US11037626B2
公开(公告)日：2021-06-15
申请号：US16432959
申请日：2019-06-06
Applicant: Samsung Electronics Co., Ltd.
Inventor： Hyun-Jin Kim , Chung-Ho Yu , Yong-Kyu Lee , Jae-Yong Jeong
IPC: G11C16/04 , G11C16/10 , G11C16/08 , G11C16/26 , H01L27/115
Abstract: A nonvolatile memory device may include a plurality of memory planes and a plurality of plane-dedicated pad sets. The plurality of memory planes may include a plurality of memory cell arrays including nonvolatile memory cells and a plurality of page buffer circuits. Each of the plurality of page buffer circuits may be connected to ones of the nonvolatile memory cells included in each of the plurality of memory cell arrays through bitlines. A plurality of plane-dedicated pad sets may be connected to the plurality of page buffer circuits through a plurality of data paths respectively such that each of the plurality plane-dedicated pad sets is dedicatedly connected to each of the plurality of page buffer circuits. A bandwidth of a data transfer may be increased by reducing a data transfer delay and supporting a parallel data transfer, and power consumption may be decreased by removing data multiplexing and/or signal routing.
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公开(公告)号：US09177660B2
公开(公告)日：2015-11-03
申请号：US14069588
申请日：2013-11-01
Applicant: Samsung Electronics Co., Ltd
Inventor： Hyun-Jun Yoon , Jae-Yong Jeong , Myung-Hoon Choi , Bo-Geun Kim , Ki-Tae Park
CPC classification number: G11C16/26 , G06F11/1048 , G06F11/1072 , G11C16/0483 , G11C29/00
Abstract: A method of operating a memory device includes changing a first read voltage, which determines a first voltage state or a second voltage state, to a voltage within a first range and determining the voltage as a first select read voltage, and changing a second read voltage, which is used to determine whether the data stored in the memory cells is a third different voltage state or a fourth different voltage state, to a voltage within a second different range and determining the voltage as a second select read voltage. The first voltage state overlaps the second voltage. The third voltage state overlaps the fourth voltage state. A difference between a voltage at an intersection of the third and fourth voltage states and the second read voltage is greater than a difference between a voltage at an intersection of the first and second voltage states and the first read voltage.
Abstract translation: 一种操作存储器件的方法包括将确定第一电压状态或第二电压状态的第一读取电压改变为第一范围内的电压并将电压确定为第一选择读取电压，并且改变第二读取电压 ，其用于确定存储在存储单元中的数据是否是第三不同电压状态或第四不同电压状态，以及第二不同范围内的电压，并将电压确定为第二选择读取电压。 第一电压状态与第二电压重叠。 第三电压状态与第四电压状态重叠。 第三和第四电压状态的交点处的电压与第二读取电压之间的差异大于第一和第二电压状态与第一读取电压的交点处的电压之间的差。
