公开(公告)号：US11094612B2

公开(公告)日：2021-08-17

申请号：US15936019

申请日：2018-03-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ju-Il Choi ,  Kwang-Jin Moon ,  Byung-Lyul Park ,  Jin-Ho An ,  Atsushi Fujisaki

IPC: H01L23/48 ,  H01L23/00 ,  H01L21/768 ,  H01L23/532 ,  H01L25/065 ,  H01L25/18

Abstract: A semiconductor device can include a substrate that has a surface. A via structure can extend through the substrate toward the surface of the substrate, where the via structure includes an upper surface. A pad structure can be on the surface of the substrate, where the pad structure can include a lower surface having at least one protrusion that is configured to protrude toward the upper surface of the via structure.

公开(公告)号：US20170051424A1

公开(公告)日：2017-02-23

申请号：US15234687

申请日：2016-08-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Atsushi Fujisaki ,  Ju-II Choi ,  Kun-Sang Park ,  Byung-Lyul Park ,  Ji-Soon Park

IPC: C25D5/02 ,  C25D21/12

CPC classification number: C25D21/12 ,  C25D17/008

Abstract: A shielding unit for a plating apparatus may include a shielding plate, a controlling plate and a rotary actuator. The shielding plate may have a plurality of holes configured to permit a passage of an electrolyte therethrough. The controlling plate may make contact with the shielding plate. The controlling plate may have a plurality of controlling holes for controlling an opening ratio of the plurality of holes of the shielding plate. The rotary actuator may rotate the controlling plate to control the opening ratio of the plurality of holes shielding plate.

Abstract translation: 电镀装置的屏蔽单元可以包括屏蔽板，控制板和旋转致动器。 屏蔽板可以具有多个构造成允许电解液通过其中的孔。 控制板可以与屏蔽板接触。 控制板可以具有用于控制屏蔽板的多个孔的开口率的多个控制孔。 旋转致动器可旋转控制板以控制多个孔屏蔽板的开口率。

公开(公告)号：US20140199810A1

公开(公告)日：2014-07-17

申请号：US14153545

申请日：2014-01-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jin-Ho Park ,  Pil-Kyu Kang ,  Tae-Yeong Kim ,  Byung-Lyul Park ,  Jum-Yong Park ,  Kyu-Ha Lee ,  Deok-Young Jung ,  Gil-Heyun Choi

IPC: H01L23/00

CPC classification number: H01L25/0657 ,  H01L21/6836 ,  H01L21/76898 ,  H01L23/3128 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68381 ,  H01L2224/03002 ,  H01L2224/0401 ,  H01L2224/05568 ,  H01L2224/05624 ,  H01L2224/06181 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/16146 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/12044 ,  H01L2924/00014 ,  H01L2924/0665 ,  H01L2924/00

Abstract: A fabricating method for a semiconductor device is provided. The fabricating method includes providing a first wafer, forming a sacrificial layer on the first wafer, forming a release layer on the sacrificial layer, forming an adhesive layer on the release layer, and placing a second wafer on the adhesive layer and bonding the first wafer to the second wafer.

Abstract translation: 提供了一种用于半导体器件的制造方法。 制造方法包括提供第一晶片，在第一晶片上形成牺牲层，在牺牲层上形成剥离层，在剥离层上形成粘合剂层，将第二晶片放置在粘合剂层上，并将第一晶片 到第二晶片。

公开(公告)号：US08691692B2

公开(公告)日：2014-04-08

申请号：US13966531

申请日：2013-08-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dong-Chan Lim ,  Gilheyun Choi ,  Kwangjin Moon ,  Deok-Young Jung ,  Byung-Lyul Park ,  Dosun Lee

IPC: H01L21/4763 ,  H01L21/44

CPC classification number: H01L21/76802 ,  H01L21/76898 ,  H01L23/481 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/0401 ,  H01L2224/05025 ,  H01L2224/1147 ,  H01L2224/13025 ,  H01L2224/13082 ,  H01L2224/13099 ,  H01L2224/13124 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2924/0001 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/00014 ,  H01L2924/00

Abstract: Provided are a semiconductor chip and a method of manufacturing the same. The semiconductor chip includes a substrate having a first side and a second side facing each other, and a through electrode being disposed in a hole penetrating the substrate, wherein an opening surrounded by the through electrode is disposed in the hole, wherein the opening comprises a first end adjacent to the first side of the substrate and a second end adjacent to the second side of the substrate.

Abstract translation: 提供一种半导体芯片及其制造方法。 半导体芯片包括具有彼此相对的第一侧和第二侧的基板，以及设置在穿透基板的孔中的贯通电极，其中，由贯通电极包围的开口设置在孔中，其中，开口包括 与基板的第一侧相邻的第一端和与基板的第二侧相邻的第二端。

公开(公告)号：US09691685B2

公开(公告)日：2017-06-27

申请号：US15163995

申请日：2016-05-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyu-Ha Lee ,  Hyung-Jun Jeon ,  Jum-Yong Park ,  Byung-Lyul Park ,  Ji-Soon Park ,  Jin-Ho An ,  Jin-Ho Chun

IPC: H01L23/544 ,  H01L23/48 ,  H01L23/00 ,  H01L23/532 ,  H01L21/768 ,  H01L21/78

CPC classification number: H01L23/481 ,  H01L21/76852 ,  H01L21/76898 ,  H01L21/78 ,  H01L23/291 ,  H01L23/293 ,  H01L23/31 ,  H01L23/3192 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266 ,  H01L23/544 ,  H01L24/02 ,  H01L24/05 ,  H01L24/13 ,  H01L2223/5446 ,  H01L2224/02372 ,  H01L2224/0239 ,  H01L2224/05568 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05647 ,  H01L2224/06151 ,  H01L2224/06156 ,  H01L2224/06181 ,  H01L2224/13023 ,  H01L2224/13024 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/14181 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/94 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/00014 ,  H01L2224/11 ,  H01L2224/03 ,  H01L2924/014

Abstract: A semiconductor device includes a substrate having a die region and a scribe region surrounding the die region, a plurality of via structures penetrating through the substrate in the die region, a portion of the via structure being exposed over a surface of the substrate, and a protection layer pattern structure provided on the surface of the substrate surrounding a sidewall of the exposed portion of the via structure and having a protruding portion covering at least a portion of the scribe region adjacent to the via structure.

公开(公告)号：US20160163590A1

公开(公告)日：2016-06-09

申请号：US14956869

申请日：2015-12-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Deokyoung Jung ,  Seong-Min Son ,  Jin-Ho An ,  Byung-Lyul Park ,  Ji-Soon Park ,  Ho-Jin Lee

IPC: H01L21/768

CPC classification number: H01L21/76898 ,  H01L21/6835 ,  H01L24/03 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68381 ,  H01L2224/03002 ,  H01L2224/034 ,  H01L2224/0557 ,  H01L2224/11002 ,  H01L2224/114 ,  H01L2224/13025 ,  H01L2924/00014 ,  H01L2224/13099 ,  H01L2224/05599

Abstract: Disclosed is a method of manufacturing a semiconductor device. A preliminary wafer-carrier assembly is formed in such a way that a wafer structure having a plurality of via structures is adhered to a light-penetrating carrier by a photodegradable adhesive. A wafer-carrier assembly having an optical shielding layer for inhibiting or preventing a light penetration is formed such that the wafer structure, the carrier and the adhesive are covered with the optical shielding layer except for the backside of the wafer structure through which the via structures are exposed. An interconnector is formed on the backside of the wafer structure such that the via structures make contact with the interconnector, and the wafer structure and the carrier are separated from each other by irradiating a light to the wafer-carrier assembly. Accordingly, the adhesive is inhibited or prevented from being dissolved during a plasma process on the wafer-carrier assembly.

Abstract translation: 公开了半导体器件的制造方法。 初步的晶片载体组件形成为具有多个通路结构的晶片结构通过可光降解的粘合剂粘附到透光载体上。 形成具有用于抑制或防止光穿透的光学屏蔽层的晶片载体组件，使得晶片结构，载体和粘合剂被除了晶片结构的背面之外的光学屏蔽层覆盖，通过该晶片结构， 被暴露。 在晶片结构的背面形成互连器，使得通孔结构与互连器接触，并且通过向晶片载体组件照射光而使晶片结构和载体彼此分离。 因此，在晶片载体组件的等离子体处理中，粘合剂被抑制或防止溶解。

公开(公告)号：US20160141282A1

公开(公告)日：2016-05-19

申请号：US14940621

申请日：2015-11-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Joo-Hee Jang ,  Pil-Kyu Kang ,  Seok-Ho Kim ,  Tae-Yeong Kim ,  Hyo-Ju Kim ,  Byung-Lyul Park ,  Jum-Yong Park ,  Jin-Ho An ,  Kyu-Ha Lee ,  Yi-Koan Hong

IPC: H01L25/00 ,  H01L21/321

CPC classification number: H01L25/50 ,  H01L21/76829 ,  H01L21/76831 ,  H01L21/76832 ,  H01L21/76885 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266 ,  H01L23/53295 ,  H01L27/14621 ,  H01L27/14623 ,  H01L27/14627 ,  H01L27/14634 ,  H01L27/14636 ,  H01L27/14643 ,  H01L27/1469 ,  H01L2224/0508 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05186 ,  H01L2224/05547 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/08121 ,  H01L2924/0002 ,  H01L2924/00 ,  H01L2924/04941 ,  H01L2924/04953

Abstract: A first insulating layer is formed on a substrate. An opening is formed in the first insulating layer. A barrier layer is formed on the first insulating layer and conforming to sidewalls of the first insulating layer in the opening, and a conductive layer is formed on the barrier layer. Chemical mechanical polishing is performed to expose the first insulating layer and leave a barrier layer pattern in the opening and a conductive layer pattern on the barrier layer pattern in the opening, wherein a portion of the conductive layer pattern protrudes above an upper surface of the insulating layer and an upper surface of the barrier layer pattern. A second insulating layer is formed on the first insulating layer, the barrier layer pattern and the conductive layer pattern and planarized to expose the conductive layer pattern. A second substrate may be bonded to the exposed conductive layer pattern.

Abstract translation: 在基板上形成第一绝缘层。 在第一绝缘层中形成开口。 阻挡层形成在第一绝缘层上并与开口中的第一绝缘层的侧壁一致，并且在阻挡层上形成导电层。 执行化学机械抛光以露出第一绝缘层并在开口中留下阻挡层图案，并且在开口中的阻挡层图案上具有导电层图案，其中导电层图案的一部分突出于绝缘体的上表面上方 层和阻挡层图案的上表面。 在第一绝缘层，阻挡层图案和导电层图案上形成第二绝缘层，并平坦化以暴露导电层图案。 第二衬底可以结合到暴露的导电层图案。

公开(公告)号：US09287251B2

公开(公告)日：2016-03-15

申请号：US14794561

申请日：2015-07-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Pil-Kyu Kang ,  Seok-Ho Kim ,  Tae-Yeong Kim ,  Hyo-Ju Kim ,  Byung-Lyul Park ,  Yeun-Sang Park ,  Jin-Ho An ,  Ho-Jin Lee ,  Joo-Hee Jang ,  Deok-Young Jung

IPC: H01L21/00 ,  H01L25/00 ,  H01L21/768 ,  H01L23/00

CPC classification number: H01L25/50 ,  H01L21/76831 ,  H01L23/5226 ,  H01L24/03 ,  H01L24/05 ,  H01L24/08 ,  H01L24/80 ,  H01L2224/03462 ,  H01L2224/03616 ,  H01L2224/05022 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05157 ,  H01L2224/05166 ,  H01L2224/05176 ,  H01L2224/05181 ,  H01L2224/05184 ,  H01L2224/05186 ,  H01L2224/05547 ,  H01L2224/05571 ,  H01L2224/05647 ,  H01L2224/08121 ,  H01L2224/08147 ,  H01L2224/80013 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2924/00014 ,  H01L2924/049 ,  H01L2924/04953 ,  H01L2924/04941 ,  H01L2924/00012

Abstract: In a method, a first opening is formed in a first insulating interlayer on a first substrate. A first conductive pattern structure contacting a first diffusion prevention insulation pattern and having a planarized top surface is formed in the first opening. Likewise, a second conductive pattern structure contacting a second diffusion prevention insulation pattern is formed in a second insulating interlayer on a second substrate. A plasma treatment process is performed on at least one of the first and second substrates having the first and second conductive pattern structures thereon, respectively. The first and second conductive pattern structures are contacted to each other to bond the first and second substrates.

Abstract translation: 在一种方法中，第一开口形成在第一基板上的第一绝缘中间层中。 在第一开口中形成有与第一扩散防止绝缘图案接触并具有平坦化顶表面的第一导电图案结构。 类似地，在第二基板上的第二绝缘中间层中形成接触第二扩散防止绝缘图案的第二导电图案结构。 在其上分别具有第一和第二导电图案结构的第一和第二基板中的至少一个上执行等离子体处理工艺。 第一和第二导电图案结构彼此接触以接合第一和第二基板。

公开(公告)号：US20160020197A1

公开(公告)日：2016-01-21

申请号：US14794561

申请日：2015-07-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Pil-Kyu Kang ,  Seok-Ho Kim ,  Tae-Yeong Kim ,  Hyo-Ju Kim ,  Byung-Lyul Park ,  Yeun-Sang Park ,  Jin-Ho An ,  Ho-Jin Lee ,  Joo-Hee Jang ,  Deok-Young Jung

IPC: H01L25/00 ,  H01L23/00 ,  H01L21/768

CPC classification number: H01L25/50 ,  H01L21/76831 ,  H01L23/5226 ,  H01L24/03 ,  H01L24/05 ,  H01L24/08 ,  H01L24/80 ,  H01L2224/03462 ,  H01L2224/03616 ,  H01L2224/05022 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05157 ,  H01L2224/05166 ,  H01L2224/05176 ,  H01L2224/05181 ,  H01L2224/05184 ,  H01L2224/05186 ,  H01L2224/05547 ,  H01L2224/05571 ,  H01L2224/05647 ,  H01L2224/08121 ,  H01L2224/08147 ,  H01L2224/80013 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2924/00014 ,  H01L2924/049 ,  H01L2924/04953 ,  H01L2924/04941 ,  H01L2924/00012

Abstract: In a method, a first opening is formed in a first insulating interlayer on a first substrate. A first conductive pattern structure contacting a first diffusion prevention insulation pattern and having a planarized top surface is formed in the first opening. Likewise, a second conductive pattern structure contacting a second diffusion prevention insulation pattern is formed in a second insulating interlayer on a second substrate, plasma treatment process is performed on at least one of the first and second substrates having the first and second conductive pattern structures thereon, respectively. The first and second conductive pattern structures are contacted to each other to bond the first and second substrates.

Abstract translation: 在一种方法中，第一开口形成在第一基板上的第一绝缘中间层中。 在第一开口中形成有与第一扩散防止绝缘图案接触并具有平坦化顶表面的第一导电图案结构。 类似地，在第二基板上的第二绝缘中间层中形成接触第二扩散防止绝缘图案的第二导电图案结构，在其上具有第一和第二导电图案结构的第一和第二基板中的至少一个上执行等离子体处理工艺， ， 分别。 第一和第二导电图案结构彼此接触以接合第一和第二基板。

公开(公告)号：US20140048952A1

公开(公告)日：2014-02-20

申请号：US13943828

申请日：2013-07-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyu-Ha Lee ,  Pil-Kyu Kang ,  Tae-Yeong Kim ,  Ho-Jin Lee ,  Byung-Lyul Park ,  Gil-Heyun Choi

IPC: H01L23/538 ,  H01L23/485

CPC classification number: H01L23/5384 ,  H01L21/6836 ,  H01L21/76834 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/485 ,  H01L23/525 ,  H01L23/53238 ,  H01L24/00 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L2224/02331 ,  H01L2224/02372 ,  H01L2224/03002 ,  H01L2224/0346 ,  H01L2224/0347 ,  H01L2224/0401 ,  H01L2224/05024 ,  H01L2224/05027 ,  H01L2224/0508 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05176 ,  H01L2224/05181 ,  H01L2224/05184 ,  H01L2224/05186 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05655 ,  H01L2224/06182 ,  H01L2224/13111 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16145 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/13091 ,  H01L2924/00 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/01074

Abstract: Semiconductor device including through via structure and redistribution structures is provided. The semiconductor device may include internal circuits on a first side of a substrate, a through via structure vertically penetrating the substrate to be electrically connected to one of the internal circuits, a redistribution structure on a second side of the substrate and electrically connected to the through via structure, and an insulating layer between the second side of the substrate and the redistribution structure. The redistribution structure may include a redistribution barrier layer and a redistribution metal layer, and the redistribution barrier layer may extend on a bottom surface of the redistribution metal layer and may partially surround a side of the redistribution metal layer.

Abstract translation: 提供了包括通孔结构和再分配结构的半导体器件。 半导体器件可以包括在衬底的第一侧上的内部电路，垂直穿过衬底以与内部电路中的一个电连接的通孔结构，在衬底的第二侧上的再分配结构，并且电连接到通孔 通孔结构，以及在基板的第二面和再分布结构之间的绝缘层。 再分布结构可以包括再分配阻挡层和再分布金属层，再分布阻挡层可以在再分布金属层的底表面上延伸并且可以部分地围绕再分布金属层的一侧。