公开(公告)号：US20180158824A1

公开(公告)日：2018-06-07

申请号：US15867329

申请日：2018-01-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ki-Il KIM ,  Jung-gun You ,  Gi-gwan Park

IPC: H01L27/092 ,  H01L29/06 ,  H01L21/8238

CPC classification number: H01L27/0924 ,  H01L21/823821 ,  H01L21/823878 ,  H01L29/0649 ,  H01L29/0657

Abstract: An integrated circuit device includes a double-humped protrusion protruding from a surface of an inter-device isolation region. To manufacture the integrated circuit device, a plurality of grooves are formed in the inter-device isolation region of a substrate, a recess is formed by partially removing a surface of the substrate between the plurality of grooves, at least one fin-type active area is formed in a device region by etching the substrate in the device region and the inter-device isolation region, and the double-humped protrusion is formed from the surface of the substrate in the inter-device isolation region.

公开(公告)号：US09859393B2

公开(公告)日：2018-01-02

申请号：US15401659

申请日：2017-01-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yong-suk Tak ,  Tae-jong Lee ,  Hyun-seung Kim ,  Bon-young Koo ,  Ki-yeon Park ,  Gi-gwan Park ,  Mi-seon Park

IPC: H01L29/76 ,  H01L29/49 ,  H01L23/535 ,  H01L21/768 ,  H01L23/532 ,  H01L29/78 ,  H01L21/8234

CPC classification number: H01L29/4983 ,  H01L21/76805 ,  H01L21/76843 ,  H01L21/76895 ,  H01L21/823425 ,  H01L21/823468 ,  H01L21/823475 ,  H01L23/485 ,  H01L23/5329 ,  H01L23/535 ,  H01L29/41791 ,  H01L29/66795 ,  H01L29/7855 ,  H01L29/7856

Abstract: A device includes: a gate line on an active region of a substrate, a pair of source/drain regions in the active region on both sides of the gate line, a contact plug on at least one source/drain region out of the pair of source/drain regions; and a multilayer-structured insulating spacer between the gate line and the contact plug. The multilayer-structured insulating spacer may include an oxide layer, a first carbon-containing insulating layer covering a first surface of the oxide layer adjacent to the gate line, and a second carbon-containing insulating layer covering a second surface of the oxide layer, opposite to the first surface of the oxide layer, adjacent to the contact plug.

公开(公告)号：US11728345B2

公开(公告)日：2023-08-15

申请号：US17345090

申请日：2021-06-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dong-chan Suh ,  Gi-gwan Park ,  Dong-woo Kim ,  Dong-suk Shin

IPC: H01L27/092 ,  H01L21/8238 ,  H01L29/165 ,  H01L29/66 ,  H01L29/04 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786

CPC classification number: H01L27/0924 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823878 ,  H01L27/092 ,  H01L29/045 ,  H01L29/0665 ,  H01L29/165 ,  H01L29/42392 ,  H01L29/6656 ,  H01L29/66545 ,  H01L29/78696

Abstract: A semiconductor device includes a substrate including a first region and a second region, fin type active areas extending in a first direction away from the substrate in each of the first and second regions, a plurality of nanosheets extending parallel to an upper surface of the fin type active areas and being spaced apart from the upper surface of the fin type active areas, a gate extending over the fin type active areas in a second direction crossing the first direction, a gate dielectric layer interposed between the gate and each of the nanosheets, first source and drain regions included in the first region and second source and drain regions included in the second region, and insulating spacers interposed between the fin type active areas and the nanosheets, wherein air spacers are interposed between the insulating spacers and the first source and drain regions.

公开(公告)号：US10361309B2

公开(公告)日：2019-07-23

申请号：US15404697

申请日：2017-01-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jae-hoon Lee ,  Gi-gwan Park ,  Tae-young Kim

IPC: H01L29/78 ,  H01L29/08 ,  H01L29/15 ,  H01L29/267 ,  H01L29/20 ,  H01L29/22 ,  H01L29/16 ,  H01L29/66

Abstract: A semiconductor device includes a substrate including a fin-shaped active region that protrudes from the substrate, a gate insulating film covering a top surface and both side walls of the fin-shaped active region, a gate electrode on the top surface and the both side walls of the fin-shaped active region and covering the gate insulating film, one pair of insulating spacers on both side walls of the gate electrode, one pair of source/drain region on the fin-shaped active region and located on both sides of the gate electrode, and a lower buffer layer between the fin-shaped active region the source/drain region. The source/drain regions include a compound semiconductor material including atoms from different groups. The lower buffer layer includes a compound semiconductor material that is amorphous and includes atoms from different groups.

公开(公告)号：US10361202B2

公开(公告)日：2019-07-23

申请号：US15611893

申请日：2017-06-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dong-chan Suh ,  Gi-gwan Park ,  Dong-woo Kim ,  Dong-suk Shin

IPC: H01L29/66 ,  H01L27/092 ,  H01L21/8238 ,  H01L29/165 ,  H01L29/04 ,  H01L29/06

Abstract: A semiconductor device includes a substrate including a first region and a second region, fin type active areas extending in a first direction away from the substrate in each of the first and second regions, a plurality of nanosheets extending parallel to an upper surface of the fin type active areas and being spaced apart from the upper surface of the fin type active areas, a gate extending over the fin type active areas in a second direction crossing the first direction, a gate dielectric layer interposed between the gate and each of the nanosheets, first source and drain regions included in the first region and second source and drain regions included in the second region, and insulating spacers interposed between the fin type active areas and the nanosheets, wherein air spacers are interposed between the insulating spacers and the first source and drain regions.

公开(公告)号：US10312341B2

公开(公告)日：2019-06-04

申请号：US15824083

申请日：2017-11-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ha-jin Lim ,  Gi-gwan Park ,  Weon-hong Kim

IPC: H01L29/49 ,  H01L29/78 ,  H01L21/8234 ,  H01L29/51 ,  H01L27/088 ,  H01L29/423 ,  H01L27/092 ,  H01L21/8238

Abstract: An integrated circuit device includes a first gate stack formed on a first high dielectric layer and comprising a first work function adjustment metal containing structure and a second gate stack formed on a second high dielectric layer and comprising a second work function adjustment metal containing structure having an oxygen content that is greater than that of the first work function adjustment metal containing structure.

公开(公告)号：US09728463B2

公开(公告)日：2017-08-08

申请号：US15209093

申请日：2016-07-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ha-jin Lim ,  Gi-gwan Park ,  Sang-yub Ie ,  Jong-han Lee ,  Jeong-hyuk Yim ,  Hye-ri Hong

IPC: H01L21/8234 ,  H01L29/66 ,  H01L21/02 ,  H01L21/67

CPC classification number: H01L21/823462 ,  H01L21/02123 ,  H01L21/02271 ,  H01L21/02318 ,  H01L21/02348 ,  H01L21/02356 ,  H01L21/02362 ,  H01L21/28185 ,  H01L21/3003 ,  H01L21/67207 ,  H01L29/66795

Abstract: Methods of manufacturing a semiconductor device are provided. The methods may include forming a fin-type active region protruding from a substrate and forming a gate insulating film covering a top surface and both sidewalls of the fin-type active region. The gate insulating film may include a high-k dielectric film. The methods may also include forming a metal-containing layer on the gate insulating film, forming a silicon capping layer containing hydrogen atoms on the metal-containing layer, removing a portion of the hydrogen atoms contained in the silicon capping layer, removing the silicon capping layer and at least a portion of the metal-containing layer, and forming a gate electrode on the gate insulating film. The gate electrode may cover the top surface and the both sidewalls of the fin-type active region.

公开(公告)号：US12225741B2

公开(公告)日：2025-02-11

申请号：US18216041

申请日：2023-06-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dong-chan Suh ,  Gi-gwan Park ,  Dong-woo Kim ,  Dong-suk Shin

IPC: H01L27/092

Abstract: A semiconductor device includes a substrate including a first region and a second region, fin type active areas extending in a first direction away from the substrate in each of the first and second regions, a plurality of nanosheets extending parallel to an upper surface of the fin type active areas and being spaced apart from the upper surface of the fin type active areas, a gate extending over the fin type active areas in a second direction crossing the first direction, a gate dielectric layer interposed between the gate and each of the nanosheets, first source and drain regions included in the first region and second source and drain regions included in the second region, and insulating spacers interposed between the fin type active areas and the nanosheets, wherein air spacers are interposed between the insulating spacers and the first source and drain regions.

公开(公告)号：US11038062B2

公开(公告)日：2021-06-15

申请号：US16416725

申请日：2019-05-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jae-hoon Lee ,  Gi-gwan Park ,  Tae-young Kim

IPC: H01L29/78 ,  H01L29/08 ,  H01L29/15 ,  H01L29/267 ,  H01L29/20 ,  H01L29/22 ,  H01L29/16 ,  H01L29/66

Abstract: A semiconductor device includes a substrate including a fin-shaped active region that protrudes from the substrate, a gate insulating film covering a top surface and both side walls of the fin-shaped active region, a gate electrode on the top surface and the both side walls of the fin-shaped active region and covering the gate insulating film, one pair of insulating spacers on both side walls of the gate electrode, one pair of source/drain region on the fin-shaped active region and located on both sides of the gate electrode, and a lower buffer layer between the fin-shaped active region the source/drain region. The source/drain regions include a compound semiconductor material including atoms from different groups. The lower buffer layer includes a compound semiconductor material that is amorphous and includes atoms from different groups.

公开(公告)号：US20190273159A1

公开(公告)日：2019-09-05

申请号：US16416725

申请日：2019-05-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jae-hoon LEE ,  Gi-gwan Park ,  Tae-Young Kim

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/20 ,  H01L29/08 ,  H01L29/22 ,  H01L29/267 ,  H01L29/15 ,  H01L29/16

Abstract: A semiconductor device includes a substrate including a fin-shaped active region that protrudes from the substrate, a gate insulating film covering a top surface and both side walls of the fin-shaped active region, a gate electrode on the top surface and the both side walls of the fin-shaped active region and covering the gate insulating film, one pair of insulating spacers on both side walls of the gate electrode, one pair of source/drain region on the fin-shaped active region and located on both sides of the gate electrode, and a lower buffer layer between the fin-shaped active region the source/drain region. The source/drain regions include a compound semiconductor material including atoms from different groups. The lower buffer layer includes a compound semiconductor material that is amorphous and includes atoms from different groups.