公开(公告)号：US09768266B2

公开(公告)日：2017-09-19

申请号：US14796569

申请日：2015-07-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kwang Soo Seol ,  Chanjin Park ,  Kihyun Hwang ,  Hanmei Choi ,  Sunghoi Hur ,  Wansik Hwang ,  Toshiro Nakanishi ,  Kwangmin Park ,  Juyul Lee

IPC: H01L29/423 ,  H01L21/3213 ,  H01L27/06 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11578 ,  H01L29/792 ,  H01L27/11582 ,  H01L29/51

CPC classification number: H01L29/42348 ,  H01L21/32137 ,  H01L27/0688 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11578 ,  H01L27/11582 ,  H01L29/511 ,  H01L29/517 ,  H01L29/792 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Three-dimensional semiconductor memory devices and methods of fabricating the same. The three-dimensional semiconductor devices include an electrode structure with sequentially-stacked electrodes disposed on a substrate, semiconductor patterns penetrating the electrode structure, and memory elements including a first pattern and a second pattern interposed between the semiconductor patterns and the electrode structure, the first pattern vertically extending to cross the electrodes and the second pattern horizontally extending to cross the semiconductor patterns.

公开(公告)号：US09537029B2

公开(公告)日：2017-01-03

申请号：US14582294

申请日：2014-12-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Beom Seok Kim ,  Bongjin Kuh ,  Jongsung Lim ,  Hanmei Choi

IPC: H01L21/02 ,  H01L31/0352 ,  H01L31/18

CPC classification number: H01L31/03529 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/26513 ,  H01L31/1804 ,  H01L31/1864 ,  Y02P70/521

Abstract: A semiconductor device includes a first semiconductor layer including a recess region and protrusions defined by the recessed region, first insulating patterns provided on the protrusions and extending to sidewalls of the protrusions, and a second semiconductor layer to fill the recess region and cover the first insulating patterns. The protrusions includes a first group of protrusions spaced apart from each other in a first direction to constitute a row and a second group of protrusions spaced from the first group of protrusions in a second direction intersecting the first direction and spaced from each other in the first direction to constitute a row. The second group of protrusions are shifted from the first group of protrusions in the first direction.

Abstract translation: 半导体器件包括：第一半导体层，包括凹陷区域和由凹陷区域限定的突起;设置在突起上并延伸到突起侧壁的第一绝缘图案;以及第二半导体层，用于填充凹陷区域并覆盖第一绝缘体 模式。 突起包括在第一方向上彼此间隔开的第一组突起，以构成一排，并且在与第一方向相交的第二方向上与第一组突起间隔开的第二组突起在第一方向上彼此间隔开 方向构成一排。 第二组突起在第一方向从第一组突起移位。

公开(公告)号：US09184302B2

公开(公告)日：2015-11-10

申请号：US13765213

申请日：2013-02-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chanjin Park ,  Kihyun Hwang ,  Dongchul Yoo ,  Junkyu Yang ,  Gyungjin Min ,  Yoochul Kong ,  Hanmei Choi

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L29/788 ,  H01L27/115 ,  H01L29/66 ,  H01L29/792 ,  H01L23/538

CPC classification number: H01L29/788 ,  H01L23/5384 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11578 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7889 ,  H01L29/792 ,  H01L29/7926 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Provided is a three dimensional semiconductor device. The device may include mold layers vertically and sequentially stacked, a conductive pattern between the stacked mold layers, a plugging pattern vertically penetrating the stacked mold layers, an intermediate pattern between the conductive pattern and the plugging pattern, and protective layer patterns between the mold layers and the plugging pattern, wherein the protective layer patterns are separated by the intermediate pattern.

Abstract translation: 提供三维半导体器件。 该装置可以包括垂直和顺序堆叠的模具层，堆叠的模具层之间的导电图案，垂直穿过堆叠的模具层的插入图案，导电图案和插入图案之间的中间图案，以及模具层之间的保护层图案 和封堵图案，其中保护层图案由中间图案分离。

公开(公告)号：US20130146961A1

公开(公告)日：2013-06-13

申请号：US13765213

申请日：2013-02-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chanjin Park ,  Kihyun Hwang ,  Dongchul Yoo ,  Junkyu Yang ,  Gyungjin Min ,  Yoochul Kong ,  Hanmei Choi

IPC: H01L29/788 ,  H01L29/792 ,  H01L23/538

CPC classification number: H01L29/788 ,  H01L23/5384 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11578 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7889 ,  H01L29/792 ,  H01L29/7926 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Provided is a three dimensional semiconductor device. The device may include mold layers vertically and sequentially stacked, a conductive pattern between the stacked mold layers, a plugging pattern vertically penetrating the stacked mold layers, an intermediate pattern between the conductive pattern and the plugging pattern, and protective layer patterns between the mold layers and the plugging pattern, wherein the protective layer patterns are separated by the intermediate pattern.

Abstract translation: 提供三维半导体器件。 该装置可以包括垂直和顺序堆叠的模具层，堆叠的模具层之间的导电图案，垂直穿过堆叠的模具层的插入图案，导电图案和插入图案之间的中间图案，以及模具层之间的保护层图案 和封堵图案，其中保护层图案由中间图案分离。

公开(公告)号：US11462553B2

公开(公告)日：2022-10-04

申请号：US17034274

申请日：2020-09-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Shinjae Kang ,  Woosung Lee ,  Jeonggil Lee ,  Hanmei Choi ,  Hauk Han

IPC: H01L27/11556 ,  H01L27/11519 ,  H01L27/11526 ,  H01L23/522 ,  H01L27/11573 ,  H01L27/11582 ,  H01L27/11565

Abstract: Semiconductor devices including a substrate including a cell array region and a through electrode region, an electrode stack on the substrate and including electrodes, vertical structures penetrating the electrode stack within the cell array region, vertical fence structures within an extension region and surrounding the through electrode region, and insulating layers being inside a perimeter defined by the vertical fence structures and being at the same level as the electrodes may be provided. The electrodes may include first protrusions protruding between the vertical fence structures in a plan view.

公开(公告)号：US11057183B2

公开(公告)日：2021-07-06

申请号：US15901093

申请日：2018-02-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yong-Hoon Son ,  Hanmei Choi ,  Kihyun Hwang

IPC: H04L5/00 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11575 ,  H01L27/11582 ,  H01L29/66 ,  H01L29/78 ,  H01L29/792 ,  H04L1/18

Abstract: A non-volatile memory structure can include a substrate extending horizontally and a filling insulating pattern extending vertically from the substrate. A plurality of active channel patterns can extend vertically from the substrate in a zig-zag pattern around a perimeter of the filling insulating pattern, where each of the active channel patterns having a respective non-circular shaped horizontal cross-section. A vertical stack of a plurality of gate lines can each extend horizontally around the filling insulating pattern and the plurality of active channel patterns.

公开(公告)号：US10999045B2

公开(公告)日：2021-05-04

申请号：US15901093

申请日：2018-02-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yong-Hoon Son ,  Hanmei Choi ,  Kihyun Hwang

IPC: H04L5/00 ,  H01L29/78 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11575 ,  H01L27/11582 ,  H01L29/66 ,  H01L29/792 ,  H04L1/18

Abstract: A non-volatile memory structure can include a substrate extending horizontally and a filling insulating pattern extending vertically from the substrate. A plurality of active channel patterns can extend vertically from the substrate in a zig-zag pattern around a perimeter of the filling insulating pattern, where each of the active channel patterns having a respective non-circular shaped horizontal cross-section. A vertical stack of a plurality of gate lines can each extend horizontally around the filling insulating pattern and the plurality of active channel patterns.

公开(公告)号：US10153292B2

公开(公告)日：2018-12-11

申请号：US15907667

申请日：2018-02-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jong Won Kim ,  Seung Hyun Lim ,  Chang Seok Kang ,  Young Woo Park ,  Dae Hoon Bae ,  Dong Seog Eun ,  Woo Sung Lee ,  Jae Duk Lee ,  Jae Woo Lim ,  Hanmei Choi

IPC: H01L27/11556 ,  H01L27/11565 ,  H01L27/11582 ,  H01L27/11521 ,  H01L27/11568 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/1157 ,  H01L27/11573 ,  H01L29/04 ,  H01L49/02

Abstract: A memory device includes a plurality of channel regions that each extend in a direction perpendicular to an upper surface of a substrate, a plurality of gate electrode layers and a plurality of insulating layers stacked on the substrate adjacent the channel regions, each of the gate electrodes extending different lengths, and a plurality of dummy channel regions adjacent first ends of the plurality of gate electrode layers, wherein the substrate includes a substrate insulating layer formed below the plurality of dummy channel regions.

公开(公告)号：US09293336B2

公开(公告)日：2016-03-22

申请号：US14258107

申请日：2014-04-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sangryol Yang ,  Soonwook Jung ,  Kyoungseob Kim ,  Youngsub You ,  Byunghong Chung ,  Hanmei Choi

IPC: H01L29/40 ,  H01L21/283 ,  H01L21/768

CPC classification number: H01L21/283 ,  H01L21/76805 ,  H01L29/401

Abstract: A semiconductor device includes a storage node contact on a substrate, and a lower electrode on the storage node contact, a lower sidewall of the lower electrode being covered by a contact residue of a same material as the storage node contact.

Abstract translation: 半导体器件包括在衬底上的存储节点接触和存储节点接触件上的下电极，下电极的下侧壁由与存储节点接触件相同的材料的接触残余物覆盖。

公开(公告)号：US08854614B2

公开(公告)日：2014-10-07

申请号：US13715099

申请日：2012-12-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jong-Hoon Kang ,  Taegon Kim ,  Hanmei Choi ,  Eunyoung Jo ,  Gonsu Kang ,  Sungho Kang ,  Sungho Heo

IPC: G01N21/00 ,  H01L21/66 ,  H01L21/68 ,  H01L21/324 ,  H01L21/67

CPC classification number: H01L21/324 ,  H01L21/67115 ,  H01L21/67288 ,  H01L21/681 ,  H01L22/10 ,  H01L22/12 ,  H01L22/20

Abstract: A method of thermally treating a wafer includes loading a wafer into a process chamber having one or more regions of uniform temperature gradient and one or more regions of non-uniform temperature gradient. A defect is detected in the wafer. The wafer is aligned to position the defect within one of the one or more regions of uniform temperature gradient. A rapid thermal process is performed on the wafer in the process chamber while the defect is positioned within one of the one or more regions of uniform temperature gradient.

Abstract translation: 一种热处理晶片的方法包括将晶片装载到具有一个或多个均匀温度梯度区域和一个或多个不均匀温度梯度区域的处理室中。 在晶片中检测到缺陷。 将晶片对准以将缺陷定位在均匀温度梯度的一个或多个区域之一内。 在处理室中的晶片上执行快速热处理，同时将缺陷定位在均匀温度梯度的一个或多个区域之一内。