公开(公告)号：US08987694B2

公开(公告)日：2015-03-24

申请号：US13729742

申请日：2012-12-28

申请人： Samsung Electronics Co., Ltd.

发明人： Jae-Jong Han ,  Kong-Soo Lee ,  Yoon-Goo Kang ,  Ho-Kyun An ,  Seong-Hoon Jeong

IPC分类号： H01L29/02 ,  H01L45/00 ,  H01L27/102 ,  H01L27/24 ,  H01L27/10

CPC分类号： H01L45/04 ,  H01L27/101 ,  H01L27/1021 ,  H01L27/2409 ,  H01L45/06 ,  H01L45/124 ,  H01L45/141 ,  H01L45/143 ,  H01L45/144

摘要： Semiconductor devices, and methods of manufacturing the same, include a field region in a semiconductor substrate to define an active region. An interlayer insulating layer is on the semiconductor substrate. A semiconductor pattern is within a hole vertically extending through the interlayer insulating layer. The semiconductor pattern is in contact with the active region. A barrier region is between the semiconductor pattern and the interlayer insulating layer. The barrier region includes a first buffer dielectric material and a barrier dielectric material. The first buffer dielectric material is between the barrier dielectric material and the semiconductor pattern, and the barrier dielectric material is spaced apart from both the semiconductor pattern and the active region.

摘要翻译： 半导体器件及其制造方法包括半导体衬底中的场区以限定有源区。 层间绝缘层位于半导体衬底上。 半导体图案在垂直延伸穿过层间绝缘层的孔内。 半导体图案与有源区域接触。 阻挡区域在半导体图案和层间绝缘层之间。 阻挡区域包括第一缓冲介电材料和阻挡介电材料。 第一缓冲电介质材料在阻挡介电材料和半导体图案之间，并且阻挡介电材料与半导体图案和有源区两者间隔开。

公开(公告)号：US09305928B2

公开(公告)日：2016-04-05

申请号：US14175076

申请日：2014-02-07

申请人： Samsung Electronics Co., Ltd.

发明人： Youngkuk Kim ,  Ho-Kyun An ,  Jaehyun Yeo ,  Badro Im ,  HanJin Lim ,  Sungho Jang ,  Insang Jeon

IPC分类号： H01L21/8242 ,  H01L27/108 ,  H01L21/8234

CPC分类号： H01L27/10894 ,  H01L21/823412 ,  H01L21/823462 ,  H01L27/10814 ,  H01L27/10861

摘要： Semiconductor devices having a silicon-germanium channel layer and methods of forming the semiconductor devices are provided. The methods may include forming a silicon-germanium channel layer on a substrate in a peripheral circuit region and sequentially forming a first insulating layer and a second insulating layer on the silicon-germanium channel layer. The methods may also include forming a conductive layer on the substrate, which includes a cell array region and the peripheral circuit region, and patterning the conductive layer to form a conductive line in the cell array region and a gate electrode in the peripheral circuit region. The first insulating layer may be formed at a first temperature and the second insulating layer may be formed at a second temperature higher than the first temperature.

摘要翻译： 提供具有硅 - 锗沟道层的半导体器件和形成半导体器件的方法。 所述方法可以包括在外围电路区域中的衬底上形成硅 - 锗沟道层，并且在硅 - 锗沟道层上依次形成第一绝缘层和第二绝缘层。 该方法还可以包括在衬底上形成导电层，该导电层包括电池阵列区域和外围电路区域，以及图案化导电层以在电池阵列区域中形成导线以及在外围电路区域中形成栅极电极。 第一绝缘层可以在第一温度下形成，并且第二绝缘层可以在高于第一温度的第二温度下形成。

公开(公告)号：US08853660B2

公开(公告)日：2014-10-07

申请号：US13668489

申请日：2012-11-05

申请人： Samsung Electronics Co., Ltd.

发明人： JaeJong Han ,  Sungun Kwon ,  Jinhye Bae ,  Kongsoo Lee ,  Seong Hoon Jeong ,  Yoongoo Kang ,  Ho-Kyun An

IPC分类号： H01L29/02

CPC分类号： H01L45/1233 ,  H01L27/1021 ,  H01L27/2409 ,  H01L27/2445 ,  H01L45/06 ,  H01L45/141

摘要： Semiconductor devices include lower interconnections, upper interconnections crossing over the lower interconnections, selection components disposed at crossing points of the lower interconnections and the upper interconnections, respectively, and memory components disposed between the selection components and the upper interconnections. Each of the selection components may include a semiconductor pattern having a first sidewall and a second sidewall. The first sidewall of the semiconductor pattern may have a first upper width and a first lower width that is greater than the first upper width. The second sidewall of the semiconductor pattern may have a second upper width and a second lower width that is substantially equal to the second upper width.

摘要翻译： 半导体器件包括下互连，在下互连上交叉的上互连，分别设置在下互连和上互连的交叉点处的选择部件以及设置在选择部件和上互连之间的存储器部件。 每个选择部件可以包括具有第一侧壁和第二侧壁的半导体图案。 半导体图案的第一侧壁可以具有大于第一上部宽度的第一上部宽度和第一下部宽度。 半导体图案的第二侧壁可以具有基本上等于第二上部宽度的第二上部宽度和第二下部宽度。