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1.发明授权Semiconductor memory devices having lower and upper interconnections, selection components and memory components 有权半导体存储器件具有下部和上部互连，选择部件和存储器部件公开(公告)号：US08853660B2
公开(公告)日：2014-10-07
申请号：US13668489
申请日：2012-11-05
发明人： JaeJong Han , Sungun Kwon , Jinhye Bae , Kongsoo Lee , Seong Hoon Jeong , Yoongoo Kang , Ho-Kyun An
IPC分类号： H01L29/02
CPC分类号： H01L45/1233 , H01L27/1021 , H01L27/2409 , H01L27/2445 , H01L45/06 , H01L45/141
摘要： Semiconductor devices include lower interconnections, upper interconnections crossing over the lower interconnections, selection components disposed at crossing points of the lower interconnections and the upper interconnections, respectively, and memory components disposed between the selection components and the upper interconnections. Each of the selection components may include a semiconductor pattern having a first sidewall and a second sidewall. The first sidewall of the semiconductor pattern may have a first upper width and a first lower width that is greater than the first upper width. The second sidewall of the semiconductor pattern may have a second upper width and a second lower width that is substantially equal to the second upper width.
摘要翻译： 半导体器件包括下互连，在下互连上交叉的上互连，分别设置在下互连和上互连的交叉点处的选择部件以及设置在选择部件和上互连之间的存储器部件。 每个选择部件可以包括具有第一侧壁和第二侧壁的半导体图案。 半导体图案的第一侧壁可以具有大于第一上部宽度的第一上部宽度和第一下部宽度。 半导体图案的第二侧壁可以具有基本上等于第二上部宽度的第二上部宽度和第二下部宽度。
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公开(公告)号：US20130146830A1
公开(公告)日：2013-06-13
申请号：US13668489
申请日：2012-11-05
发明人： JaeJong Han , Sungun Kwon , Jinhye Bae , Kongsoo Lee , Seong Hoon Jeong , Yoongoo Kang , Hy-Kyun An
CPC分类号： H01L45/1233 , H01L27/1021 , H01L27/2409 , H01L27/2445 , H01L45/06 , H01L45/141
摘要： Semiconductor devices include lower interconnections, upper interconnections crossing over the lower interconnections, selection components disposed at crossing points of the lower interconnections and the upper interconnections, respectively, and memory components disposed between the selection components and the upper interconnections. Each of the selection components may include a semiconductor pattern having a first sidewall and a second sidewall. The first sidewall of the semiconductor pattern may have a first upper width and a first lower width that is greater than the first upper width. The second sidewall of the semiconductor pattern may have a second upper width and a second lower width that is substantially equal to the second upper width.
摘要翻译： 半导体器件包括下互连，在下互连上交叉的上互连，分别设置在下互连和上互连的交叉点处的选择部件以及设置在选择部件和上互连之间的存储器部件。 每个选择部件可以包括具有第一侧壁和第二侧壁的半导体图案。 半导体图案的第一侧壁可以具有大于第一上部宽度的第一上部宽度和第一下部宽度。 半导体图案的第二侧壁可以具有基本上等于第二上部宽度的第二上部宽度和第二下部宽度。
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