公开(公告)号：US20230171950A1

公开(公告)日：2023-06-01

申请号：US17940323

申请日：2022-09-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sunguk Jang ,  Kongsoo Lee ,  Sahwan Hong

IPC: H01L27/108

CPC classification number: H01L27/10814

Abstract: A semiconductor device includes a plurality of semiconductor patterns stacked to be spaced apart from each other in a first direction, perpendicular to an upper surface of a substrate, and extending in a second direction, parallel to the upper surface of the substrate, a plurality of first conductive patterns extending in a third direction, perpendicular to the first direction and the second direction, on the plurality of semiconductor patterns, a plurality of second conductive patterns extending in the first direction on the substrate, a plurality of capacitors electrically connected to the plurality of semiconductor patterns, respectively, and at least one epitaxial layer disposed to be in contact with at least one of both end surfaces of at least one of the plurality of semiconductor patterns and including an impurity.

公开(公告)号：US10535663B2

公开(公告)日：2020-01-14

申请号：US16245307

申请日：2019-01-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jinwon Ma ,  Jun-Noh Lee ,  Dong-Hyun Im ,  Youngseok Kim ,  Kongsoo Lee

IPC: H01L27/108 ,  H01L21/768

Abstract: A method of fabricating a semiconductor device includes forming an interlayer insulating structure on a substrate, forming a contact hole that penetrates the interlayer insulating structure to expose the substrate, forming an amorphous silicon layer including a first portion and a second portion, the first portion covering a top surface of the substrate exposed by the contact hole, the second portion covering a sidewall of the contact hole, providing hydrogen atoms into the amorphous silicon layer, and crystallizing the first portion using the substrate as a seed.

公开(公告)号：US20230076270A1

公开(公告)日：2023-03-09

申请号：US17720880

申请日：2022-04-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dohee Kim ,  Sunguk Jang ,  Bongjin Kuh ,  Kongsoo Lee ,  Sahwan Hong

IPC: H01L29/06 ,  H01L27/088 ,  H01L29/786

Abstract: An integrated circuit device includes: an active region extending in a first horizontal direction on a substrate; a first transistor at a first vertical level on the active region, the first transistor including a first source/drain region having a first conductive type; and a second transistor at a second vertical level that is higher than the first vertical level on the active region, the second transistor including a second source/drain region having a second conductive type and overlapping the first source/drain region in a vertical direction, wherein the first source/drain region and the second source/drain region have different sizes.

公开(公告)号：US10211210B2

公开(公告)日：2019-02-19

申请号：US15603668

申请日：2017-05-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jinwon Ma ,  Jun-Noh Lee ,  Dong-Hyun Im ,  Youngseok Kim ,  Kongsoo Lee

IPC: H01L27/108 ,  H01L21/768

Abstract: A method of fabricating a semiconductor device includes forming an interlayer insulating structure on a substrate, forming a contact hole that penetrates the interlayer insulating structure to expose the substrate, forming an amorphous silicon layer including a first portion and a second portion, the first portion covering a top surface of the substrate exposed by the contact hole, the second portion covering a sidewall of the contact hole, providing hydrogen atoms into the amorphous silicon layer, and crystallizing the first portion using the substrate as a seed.

公开(公告)号：US10748909B2

公开(公告)日：2020-08-18

申请号：US16711833

申请日：2019-12-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jinwon Ma ,  Jun-Noh Lee ,  Dong-Hyun Im ,  Youngseok Kim ,  Kongsoo Lee

IPC: H01L27/108 ,  H01L21/768 ,  H01L23/485 ,  H01L23/532

Abstract: A method of fabricating a semiconductor device includes forming an interlayer insulating structure on a substrate, forming a contact hole that penetrates the interlayer insulating structure to expose the substrate, forming an amorphous silicon layer including a first portion and a second portion, the first portion covering a top surface of the substrate exposed by the contact hole, the second portion covering a sidewall of the contact hole, providing hydrogen atoms into the amorphous silicon layer, and crystallizing the first portion using the substrate as a seed.

公开(公告)号：US09543202B2

公开(公告)日：2017-01-10

申请号：US15060641

申请日：2016-03-04

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jamin Koo ,  Youngseok Kim ,  Kongsoo Lee ,  Goeun Bae

IPC: H01L21/44 ,  H01L21/768 ,  H01L21/285 ,  H01L23/532 ,  H01L21/28

CPC classification number: H01L21/76895 ,  H01L21/28035 ,  H01L21/288 ,  H01L21/76831 ,  H01L21/76877 ,  H01L21/76897 ,  H01L23/53271 ,  H01L27/10888

Abstract: Provided is a method of fabricating a semiconductor device, the method including forming interconnection structures extending parallel to each other on a substrate; performing a coating process and forming a liquid state silicon source material layer filling an area between the interconnection structures; performing a first annealing process, curing the liquid state silicon source material layer, and forming an amorphous silicon layer; and crystallizing the amorphous silicon layer and forming contact plugs.

Abstract translation: 提供一种制造半导体器件的方法，该方法包括在衬底上形成彼此平行延伸的互连结构; 执行涂覆工艺并形成填充所述互连结构之间的区域的液态硅源材料层; 进行第一退火处理，固化液态硅源材料层，形成非晶硅层; 并使非晶硅层结晶并形成接触塞。

公开(公告)号：US08853660B2

公开(公告)日：2014-10-07

申请号：US13668489

申请日：2012-11-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： JaeJong Han ,  Sungun Kwon ,  Jinhye Bae ,  Kongsoo Lee ,  Seong Hoon Jeong ,  Yoongoo Kang ,  Ho-Kyun An

IPC: H01L29/02

CPC classification number: H01L45/1233 ,  H01L27/1021 ,  H01L27/2409 ,  H01L27/2445 ,  H01L45/06 ,  H01L45/141

Abstract: Semiconductor devices include lower interconnections, upper interconnections crossing over the lower interconnections, selection components disposed at crossing points of the lower interconnections and the upper interconnections, respectively, and memory components disposed between the selection components and the upper interconnections. Each of the selection components may include a semiconductor pattern having a first sidewall and a second sidewall. The first sidewall of the semiconductor pattern may have a first upper width and a first lower width that is greater than the first upper width. The second sidewall of the semiconductor pattern may have a second upper width and a second lower width that is substantially equal to the second upper width.

Abstract translation: 半导体器件包括下互连，在下互连上交叉的上互连，分别设置在下互连和上互连的交叉点处的选择部件以及设置在选择部件和上互连之间的存储器部件。 每个选择部件可以包括具有第一侧壁和第二侧壁的半导体图案。 半导体图案的第一侧壁可以具有大于第一上部宽度的第一上部宽度和第一下部宽度。 半导体图案的第二侧壁可以具有基本上等于第二上部宽度的第二上部宽度和第二下部宽度。

公开(公告)号：US20200119021A1

公开(公告)日：2020-04-16

申请号：US16711833

申请日：2019-12-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jinwon MA ,  Jun-Noh Lee ,  Dong-Hyun IM ,  Youngseok Kim ,  Kongsoo Lee

IPC: H01L27/108 ,  H01L21/768 ,  H01L23/485

Abstract: A method of fabricating a semiconductor device includes forming an interlayer insulating structure on a substrate, forming a contact hole that penetrates the interlayer insulating structure to expose the substrate, forming an amorphous silicon layer including a first portion and a second portion, the first portion covering a top surface of the substrate exposed by the contact hole, the second portion covering a sidewall of the contact hole, providing hydrogen atoms into the amorphous silicon layer, and crystallizing the first portion using the substrate as a seed.

公开(公告)号：US20170345824A1

公开(公告)日：2017-11-30

申请号：US15603668

申请日：2017-05-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jinwon MA ,  Jun-Noh Lee ,  Dong-Hyun Im ,  Youngseok Kim ,  Kongsoo Lee

IPC: H01L27/108 ,  H01L21/768

CPC classification number: H01L27/10888 ,  H01L21/76805 ,  H01L21/76883 ,  H01L21/76895 ,  H01L27/10811 ,  H01L27/10855 ,  H01L27/10885

Abstract: A method of fabricating a semiconductor device includes forming an interlayer insulating structure on a substrate, forming a contact hole that penetrates the interlayer insulating structure to expose the substrate, forming an amorphous silicon layer including a first portion and a second portion, the first portion covering a top surface of the substrate exposed by the contact hole, the second portion covering a sidewall of the contact hole, providing hydrogen atoms into the amorphous silicon layer, and crystallizing the first portion using the substrate as a seed.

公开(公告)号：US09685318B2

公开(公告)日：2017-06-20

申请号：US14920922

申请日：2015-10-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Young-Lim Park ,  Wonseok Yoo ,  Hyokyoung Kim ,  Changyup Park ,  Kongsoo Lee ,  Wook-Yeol Yi ,  Hanjin Lim

IPC: H01L21/02 ,  H01L21/311 ,  H01L27/108

CPC classification number: H01L21/0217 ,  H01L21/02247 ,  H01L27/10885

Abstract: Provided is a method of forming a semiconductor device. The method can include loading a semiconductor substrate into semiconductor equipment. A base layer can be formed on the loaded semiconductor substrate by performing a base deposition process using a base source material. A first silicon layer can be formed on the base layer to a greater thickness than the base layer by performing a first silicon deposition process using a silicon source material different from the base source material. A first nitrided silicon layer can be formed by nitriding the first silicon layer using a first nitridation process. The semiconductor substrate having the first nitrided silicon layer can be unloaded from the semiconductor equipment.