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    SEMICONDUCTOR MEMORY DEVICES AND METHODS OF FABRICATING THE SAME
    1.
    发明申请
    SEMICONDUCTOR MEMORY DEVICES AND METHODS OF FABRICATING THE SAME 有权

    公开(公告)号：US20220028860A1

    公开(公告)日：2022-01-27

    申请号：US17192084

    申请日：2021-03-04

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Minsu Choi ,  Myeong-Dong Lee ,  Hyeon-Woo Jang ,  Keunnam Kim ,  Sooho Shin ,  Yoosang Hwang

    IPC: H01L27/108

    Abstract: Disclosed are a semiconductor memory device and a method of fabricating the same. The device includes a substrate including an active pattern with doped regions, a gate electrode crossing the active pattern between the doped regions, a bit line crossing the active pattern and being electrically connected to one of the doped regions, a spacer on a side surface of the bit line, a first contact coupled to another of the doped regions and spaced apart from the bit line with the spacer interposed therebetween, a landing pad on the first contact, and a data storing element on the landing pad. The another of the doped regions has a top surface, an upper side surface, and a curved top surface that extends from the top surface to the upper side surface. The first contact is in contact with the curved top surface and the upper side surface.

    Semiconductor devices and methods of fabricating the same
    3.
    发明授权
    Semiconductor devices and methods of fabricating the same 有权

    公开(公告)号：US10211091B2

    公开(公告)日：2019-02-19

    申请号：US15334469

    申请日：2016-10-26

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Myeong-Dong Lee ,  Keunnam Kim ,  Dongryul Lee ,  Minseong Choi ,  Jimin Choi ,  Yong Kwan Kim ,  Changhyun Cho ,  Yoosang Hwang

    IPC: H01L21/76 ,  H01L21/768 ,  H01L23/532 ,  H01L23/535 ,  H01L27/108

    Abstract: According to some embodiments, a semiconductor device may include gate structures on a substrate; first and second impurity regions formed in the substrate and at both sides of each of the gate structures; conductive line structures provided to cross the gate structures and connected to the first impurity regions; and contact plugs connected to the second impurity regions, respectively. For each of the conductive line structures, the semiconductor device may include a first air spacer provided on a sidewall of the conductive line structure; a first material spacer provided between the conductive line structure and the first air spacer; and an insulating pattern provided on the air spacer. The insulating pattern may include a first portion and a second portion, and the second portion may have a depth greater than that of the first portion and defines a top surface of the air spacer.

    SEMICONDUCTOR MEMORY DEVICES AND METHODS FOR MANUFACTURING THE SAME
    4.
    发明公开
    SEMICONDUCTOR MEMORY DEVICES AND METHODS FOR MANUFACTURING THE SAME 审中-公开

    公开(公告)号：US20240365532A1

    公开(公告)日：2024-10-31

    申请号：US18507204

    申请日：2023-11-13

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Tae Jin Park ,  Jun Soo Kim ,  Ji Ho Park ,  Ki Seok Lee ,  Myeong-Dong Lee ,  Ho Sang Lee

    IPC: H10B12/00

    CPC classification number: H10B12/34 ,  H10B12/053 ,  H10B12/315

    Abstract: Semiconductor memory devices including capacitors and methods for manufacturing thereof. The semiconductor memory device may include a substrate, an element isolation pattern defining an active area in the substrate, a first conductive pattern on the substrate and the element isolation pattern, and extending in a first direction, wherein the first conductive pattern is connected to a first portion of the active area, a capacitor structure on the substrate and the element isolation pattern and connected to a second portion of the active area, a gate trench defined in the substrate and the element isolation pattern and extending in a second direction, wherein a first trench width of a portion of the gate trench in the active area is greater than a second trench width of a portion of the gate trench in the element isolation pattern.

    SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
    5.
    发明公开
    SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF 审中-公开

    公开(公告)号：US20240324181A1

    公开(公告)日：2024-09-26

    申请号：US18469791

    申请日：2023-09-19

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jongmin Kim ,  Ho-Ju Song ,  Myeong-Dong Lee

    IPC: H10B12/00 ,  H01L21/768 ,  H01L23/528

    CPC classification number: H10B12/482 ,  H01L21/76877 ,  H01L23/528 ,  H10B12/03 ,  H10B12/485

    Abstract: A method of manufacturing a semiconductor device includes forming a buffer layer on a substrate including active regions and word lines, sequentially stacking a first conductive layer and a first insulating layer, forming bit line structure main parts such that each bit line main part is in contact with one or more of the active regions through a plurality of first contacts, by etching the first insulating layer and the first conductive layer, stacking first spacers, forming bit line structure expansions by etching the first spacers, the first insulating layer, and the first conductive layer, and forming second contacts such that the second contacts are in contact with the active regions, respectively. The bit line structure expansions are connected to the bit line structure main parts, respectively, and are wider than the bit line structure main parts as viewed in a plan view.

    SEMICONDUCTOR MEMORY DEVICE
    7.
    发明公开
    SEMICONDUCTOR MEMORY DEVICE 审中-公开

    公开(公告)号：US20240349491A1

    公开(公告)日：2024-10-17

    申请号：US18534400

    申请日：2023-12-08

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Myeong-Dong Lee ,  Jongmin Kim ,  Taejin Park ,  Seung-Bo Ko ,  Hui-Jung Kim

    IPC: H10B12/00

    CPC classification number: H10B12/485 ,  H10B12/482 ,  H10B12/488

    Abstract: An example semiconductor memory device includes first and second active patterns, which are extended in a first direction and are disposed side by side in a second direction. Each of the first and second active patterns includes first and second edge portions, which are spaced apart from each other in the first direction. A pair of word lines are disposed to cross each of the first and second active patterns, a pair of bit lines are disposed on each of the first and second active patterns and are extended in a third direction, and a storage node contacts on the first edge portion of the first active pattern. When measured in the second direction, a first width of the storage node contact at a first level is larger than a second width at a second level. The first level is lower than the second level.

    Semiconductor memory devices having protruding contact portions
    8.
    发明授权
    Semiconductor memory devices having protruding contact portions 有权

    公开(公告)号：US11723191B2

    公开(公告)日：2023-08-08

    申请号：US17192084

    申请日：2021-03-04

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Minsu Choi ,  Myeong-Dong Lee ,  Hyeon-Woo Jang ,  Keunnam Kim ,  Sooho Shin ,  Yoosang Hwang

    IPC: H10B12/00

    CPC classification number: H10B12/34 ,  H10B12/0335 ,  H10B12/053 ,  H10B12/315

    Abstract: Disclosed are a semiconductor memory device and a method of fabricating the same. The device includes a substrate including an active pattern with doped regions, a gate electrode crossing the active pattern between the doped regions, a bit line crossing the active pattern and being electrically connected to one of the doped regions, a spacer on a side surface of the bit line, a first contact coupled to another of the doped regions and spaced apart from the bit line with the spacer interposed therebetween, a landing pad on the first contact, and a data storing element on the landing pad. The another of the doped regions has a top surface, an upper side surface, and a curved top surface that extends from the top surface to the upper side surface. The first contact is in contact with the curved top surface and the upper side surface.

    Semiconductor devices and methods of fabricating the same
    9.
    发明授权
    Semiconductor devices and methods of fabricating the same 有权

    公开(公告)号：US10796950B2

    公开(公告)日：2020-10-06

    申请号：US16238172

    申请日：2019-01-02

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Myeong-Dong Lee ,  Keunnam Kim ,  Dongryul Lee ,  Minseong Choi ,  Jimin Choi ,  Yong Kwan Kim ,  Changhyun Cho ,  Yoosang Hwang

    IPC: H01L21/76 ,  H01L21/768 ,  H01L27/108 ,  H01L23/532 ,  H01L23/535

    Abstract: According to some embodiments, a semiconductor device may include gate structures on a substrate; first and second impurity regions formed in the substrate and at both sides of each of the gate structures; conductive line structures provided to cross the gate structures and connected to the first impurity regions; and contact plugs connected to the second impurity regions, respectively. For each of the conductive line structures, the semiconductor device may include a first air spacer provided on a sidewall of the conductive line structure; a first material spacer provided between the conductive line structure and the first air spacer; and an insulating pattern provided on the air spacer. The insulating pattern may include a first portion and a second portion, and the second portion may have a depth greater than that of the first portion and defines a top surface of the air spacer.

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