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公开(公告)号：US09728604B2
公开(公告)日：2017-08-08
申请号：US15059438
申请日：2016-03-03
发明人： Jin-Nam Kim , Rak-Hwan Kim , Byung-Hee Kim , Jong-Min Baek , Sang-Hoon Ahn , Nae-In Lee , Jong-Jin Lee , Ho-Yun Jeon , Eun-Ji Jung
IPC分类号： H01L29/08 , H01L23/532 , H01L21/768 , H01L23/522 , H01L23/528 , H01L27/088 , H01L27/12
CPC分类号： H01L29/0847 , H01L21/7682 , H01L21/76834 , H01L21/76837 , H01L21/76852 , H01L21/76862 , H01L21/76885 , H01L23/5222 , H01L23/5283 , H01L23/53223 , H01L23/53238 , H01L23/53266 , H01L23/53295 , H01L27/0886 , H01L27/1211
摘要： Semiconductor devices may include a diffusion prevention insulation pattern, a plurality of conductive patterns, a barrier layer, and an insulating interlayer. The diffusion prevention insulation pattern may be formed on a substrate, and may include a plurality of protrusions protruding upwardly therefrom. Each of the conductive patterns may be formed on each of the protrusions of the diffusion prevention insulation pattern, and may have a sidewall inclined by an angle in a range of about 80 degrees to about 135 degrees to a top surface of the substrate. The barrier layer may cover a top surface and the sidewall of each if the conductive patterns. The insulating interlayer may be formed on the diffusion prevention insulation pattern and the barrier layer, and may have an air gap between neighboring ones of the conductive patterns.
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公开(公告)号：US10734309B2
公开(公告)日：2020-08-04
申请号：US16282682
申请日：2019-02-22
发明人： Jin-Nam Kim , Tsukasa Matsuda , Rak-Hwan Kim , Byung-Hee Kim , Nae-In Lee , Jong-Jin Lee
IPC分类号： H01L23/48 , H01L23/485 , H01L21/768 , H01L23/498 , H01L23/522 , H01L23/532
摘要： A semiconductor device and a method of fabricating the same are provided. The semiconductor device includes a first interlayer insulating layer including a first trench, on a substrate a first liner layer formed along a side wall and a bottom surface of the first trench and including noble metal, the noble metal belonging to one of a fifth period and a sixth period of a periodic chart that follows numbering of International Union of Pure and Applied Chemistry (IUPAC) and belonging to one of eighth to tenth groups of the periodic chart, and a first metal wire filling the first trench on the first liner layer, a top surface of the first metal wire having a convex shape toward a bottom surface of the first trench.
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公开(公告)号：US10332791B2
公开(公告)日：2019-06-25
申请号：US15805865
申请日：2017-11-07
发明人： Ho-Yun Jeon , Rak-Hwan Kim , Byung-Hee Kim , Kyoung-Hee Nam , Jong-Jin Lee , Jae-Won Hwang
IPC分类号： H01L21/768 , H01L23/532 , H01L21/288 , H01L23/528 , H01L23/522 , H01L21/285
摘要： A semiconductor device includes an insulating interlayer disposed on a substrate, a first protection pattern, a first barrier pattern, a first adhesion pattern, and a first conductive pattern. The insulating interlayer includes a via hole and a first trench. The via hole extends through a lower portion of the insulating interlayer. The first trench is connected to the via hole and extends through an upper portion of the insulating interlayer. The first protection pattern covers a lower surface and sidewalls of the via hole and a portion of a lower surface and a lower sidewall of the first trench, and includes a conductive material. The first barrier pattern covers the protection pattern and an upper sidewall of the first trench. The first adhesion pattern covers the first barrier pattern. The first conductive pattern is disposed on the first adhesion pattern, and fills the via hale and the first trench.
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公开(公告)号：US09991203B2
公开(公告)日：2018-06-05
申请号：US15298855
申请日：2016-10-20
发明人： Rak-Hwan Kim , Byung-Hee Kim , Jin-Nam Kim , Jong-Min Baek , Nae-In Lee , Eun-Ji Jung
IPC分类号： H01L29/40 , H01L21/44 , H01L23/528 , H01L21/768 , H01L23/532
CPC分类号： H01L23/5283 , H01L21/76847 , H01L21/76877 , H01L23/53209 , H01L23/53238 , H01L23/53261 , H01L23/53266
摘要： A semiconductor device and a method of fabricating the same are provided. The semiconductor device includes an interlayer insulating film, a first trench having a first width, and a second trench having a second width, the second trench including an upper portion and a lower portion, the second width being greater than the first width, a first wire substantially filling the first trench and including a first metal, and a second wire substantially filling the second trench and including a lower wire and an upper wire, the lower wire substantially filling a lower portion of the second trench and including the first metal, and the upper wire substantially filling an upper portion of the second trench and including a second metal different from the first metal.
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公开(公告)号：US09773699B2
公开(公告)日：2017-09-26
申请号：US15000302
申请日：2016-01-19
发明人： Jong-Jin Lee , Rak-Hwan Kim , Byung-Hee Kim , Jin-Nam Kim , Tsukasa Matsuda , Wan-Soo Park , Nae-In Lee , Jae-Won Chang , Eun-Ji Jung , Jeong-Ok Cha , Jae-Won Hwang , Jung-Ha Hwang
IPC分类号： H01L21/76 , H01L21/768 , H01L23/522 , H01L23/528 , H01L23/532
CPC分类号： H01L21/76882 , H01L21/76807 , H01L21/76843 , H01L21/76864 , H01L21/76877 , H01L23/522 , H01L23/5226 , H01L23/5283 , H01L23/53238
摘要： In a method of forming a wiring structure, a lower structure is formed on a substrate. An insulating interlayer is formed on the lower structure. The insulating interlayer is partially removed to form at least one via hole and a dummy via hole. An upper portion of the insulating interlayer is partially removed to form a trench connecting the via hole and the dummy via hole. A first metal layer filling the via hole and the dummy via hole is formed. A second metal layer filling the trench is formed on the first metal layer.
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公开(公告)号：US20170358519A1
公开(公告)日：2017-12-14
申请号：US15669280
申请日：2017-08-04
发明人： Jin-Nam Kim , Tsukasa Matsuda , Rak-Hwan Kim , Byung-Hee Kim , Nae-In Lee , Jong-Jin Lee
IPC分类号： H01L23/485 , H01L23/498 , H01L21/768 , H01L23/532 , H01L23/522
CPC分类号： H01L23/485 , H01L21/7684 , H01L21/76846 , H01L21/76849 , H01L21/76882 , H01L23/49822 , H01L23/49866 , H01L23/5226 , H01L23/53209 , H01L23/53223 , H01L23/53238 , H01L23/53266 , H01L23/53276 , H01L23/5329 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device and a method of fabricating the same are provided. The semiconductor device includes a first interlayer insulating layer including a first trench, on a substrate a first liner layer formed along a side wall and a bottom surface of the first trench and including noble metal, the noble metal belonging to one of a fifth period and a sixth period of a periodic chart that follows numbering of International Union of Pure and Applied Chemistry (IUPAC) and belonging to one of eighth to tenth groups of the periodic chart, and a first metal wire filling the first trench on the first liner layer, a top surface of the first metal wire having a convex shape toward a bottom suffice of the first trench.
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公开(公告)号：US20190189744A1
公开(公告)日：2019-06-20
申请号：US16274350
申请日：2019-02-13
发明人： Jin-Nam Kim , Rak-Hwan Kim , Byung-Hee Kim , Jong-Min Baek , Sang-Hoon Ahn , Nae-In Lee , Jong-Jin Lee , Ho-Yun Jeon , Eun-Ji Jung
IPC分类号： H01L29/08 , H01L23/532 , H01L27/12 , H01L27/088 , H01L21/768 , H01L23/528 , H01L23/522
CPC分类号： H01L29/0847 , H01L21/7682 , H01L21/76834 , H01L21/76837 , H01L21/76852 , H01L21/76862 , H01L21/76885 , H01L23/5222 , H01L23/5283 , H01L23/53223 , H01L23/53238 , H01L23/53266 , H01L23/53295 , H01L27/0886 , H01L27/1211
摘要： Semiconductor devices may include a diffusion prevention insulation pattern, a plurality of conductive patterns, a barrier layer, and an insulating interlayer. The diffusion prevention insulation pattern may be formed on a substrate, and may include a plurality of protrusions protruding upwardly therefrom. Each of the conductive patterns may be formed on each of the protrusions of the diffusion prevention insulation pattern, and may have a sidewall inclined by an angle in a range of about 80 degrees to about 135 degrees to a top surface of the substrate. The barrier layer may cover a top surface and the sidewall of each if the conductive patterns. The insulating interlayer may be formed on the diffusion prevention insulation pattern and the barrier layer, and may have an air gap between neighboring ones of the conductive patterns.
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公开(公告)号：US10217820B2
公开(公告)日：2019-02-26
申请号：US15632884
申请日：2017-06-26
发明人： Jin-Nam Kim , Rak-Hwan Kim , Byung-Hee Kim , Jong-Min Baek , Sang-Hoon Ahn , Nae-In Lee , Jong-Jin Lee , Ho-Yun Jeon , Eun-Ji Jung
IPC分类号： H01L29/08 , H01L23/532 , H01L21/768 , H01L23/522 , H01L23/528 , H01L27/088 , H01L27/12
摘要： Semiconductor devices may include a diffusion prevention insulation pattern, a plurality of conductive patterns, a barrier layer, and an insulating interlayer. The diffusion prevention insulation pattern may be formed on a substrate, and may include a plurality of protrusions protruding upwardly therefrom. Each of the conductive patterns may be formed on each of the protrusions of the diffusion prevention insulation pattern, and may have a sidewall inclined by an angle in a range of about 80 degrees to about 135 degrees to a top surface of the substrate. The barrier layer may cover a top surface and the sidewall of each if the conductive patterns. The insulating interlayer may be formed on the diffusion prevention insulation pattern and the barrier layer, and may have an air gap between neighboring ones of the conductive patterns.
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公开(公告)号：US10700164B2
公开(公告)日：2020-06-30
申请号：US16274350
申请日：2019-02-13
发明人： Jin-Nam Kim , Rak-Hwan Kim , Byung-Hee Kim , Jong-Min Baek , Sang-Hoon Ahn , Nae-In Lee , Jong-Jin Lee , Ho-Yun Jeon , Eun-Ji Jung
IPC分类号： H01L29/08 , H01L23/532 , H01L21/768 , H01L23/522 , H01L23/528 , H01L27/088 , H01L27/12
摘要： Semiconductor devices may include a diffusion prevention insulation pattern, a plurality of conductive patterns, a barrier layer, and an insulating interlayer. The diffusion prevention insulation pattern may be formed on a substrate, and may include a plurality of protrusions protruding upwardly therefrom. Each of the conductive patterns may be formed on each of the protrusions of the diffusion prevention insulation pattern, and may have a sidewall inclined by an angle in a range of about 80 degrees to about 135 degrees to a top surface of the substrate. The barrier layer may cover a top surface and the sidewall of each if the conductive patterns. The insulating interlayer may be formed on the diffusion prevention insulation pattern and the barrier layer, and may have an air gap between neighboring ones of the conductive patterns.
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公开(公告)号：US20180158730A1
公开(公告)日：2018-06-07
申请号：US15805865
申请日：2017-11-07
发明人： Ho-Yun Jeon , Rak-Hwan Kim , Byung-Hee Kim , Kyoung-Hee Nam , Jong-Jin Lee , Jae-Won Hwang
IPC分类号： H01L21/768 , H01L23/532 , H01L23/528 , H01L23/522
CPC分类号： H01L21/76865 , H01L21/2855 , H01L21/28556 , H01L21/2885 , H01L21/7681 , H01L21/76811 , H01L21/76813 , H01L21/76816 , H01L21/7684 , H01L21/76846 , H01L21/76873 , H01L21/76877 , H01L23/5226 , H01L23/5283 , H01L23/53223 , H01L23/53238
摘要： A semiconductor device includes an insulating interlayer disposed on a substrate, a first protection pattern, a first barrier pattern, a first adhesion pattern, and a first conductive pattern. The insulating interlayer includes a via hole and a first trench, The via hole extends through a lower portion of the insulating interlayer. The first trench is connected to the via hole and extends through an upper portion of the insulating interlayer, The first protection pattern covers a lower surface and sidewalls of the via hole and a portion of a lower surface and a lower sidewall of the first trench, and includes a conductive material. The first barrier pattern covers the protection pattern and an upper sidewall of the first trench. The first adhesion pattern covers the first barrier pattern. The first conductive pattern is disposed on the first adhesion pattern, and fills the via hale and the first trench.
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