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    Semiconductor memory devices and memory systems including the same
    1.
    发明授权
    Semiconductor memory devices and memory systems including the same 有权

    公开(公告)号：US10191805B2

    公开(公告)日：2019-01-29

    申请号：US15204536

    申请日：2016-07-07

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Sang-Uhn Cha ,  Hoi-Ju Chung

    IPC: G06F11/10 ,  G11C29/52 ,  G11C29/04

    Abstract: A semiconductor memory device includes a memory cell array, an error correction circuit and a control logic circuit. The error correction circuit performs an error correction code (ECC) encoding on write data to be stored in the memory cell array, and performs an ECC decoding on read data from the memory cell array. The control logic circuit controls access to the memory cell array and generates an engine configuration selection signal based on a command. The error correction circuit reconfigures a number of units for which ECC including the ECC encoding and the ECC decoding is performed, in response to the engine configuration selection signal.

    Semiconductor memory devices, memory systems and methods of operating semiconductor memory devices
    4.
    发明授权
    Semiconductor memory devices, memory systems and methods of operating semiconductor memory devices 有权

    公开(公告)号：US10811078B2

    公开(公告)日：2020-10-20

    申请号：US16779194

    申请日：2020-01-31

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Sang-Uhn Cha ,  Hyun-Gi Kim ,  Hoon Sin ,  Ye-Sin Ryu ,  In-Woo Jun

    IPC: G01C7/00 ,  G11C11/406 ,  G06F11/10

    Abstract: A semiconductor memory device includes a memory cell array, an error correction code (ECC) engine, a refresh control circuit, a scrubbing control circuit and a control logic circuit. The refresh control circuit generates refresh row addresses for refreshing a memory region on memory cell rows in response to a first command received from a memory controller. The scrubbing control circuit counts the refresh row addresses and generates a scrubbing address for performing a scrubbing operation on a first memory cell row of the memory cell rows whenever the scrubbing control circuit counts N refresh row addresses of the refresh row addresses. The ECC engine reads first data corresponding to a first codeword, from at least one sub-page in the first memory cell row, corrects at least one error bit in the first codeword and writes back the corrected first codeword in a corresponding memory location.

    Semiconductor memory devices, memory systems and methods of operating semiconductor memory devices
    6.
    发明授权
    Semiconductor memory devices, memory systems and methods of operating semiconductor memory devices 有权

    公开(公告)号：US10573356B2

    公开(公告)日：2020-02-25

    申请号：US15851197

    申请日：2017-12-21

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Sang-Uhn Cha ,  Young-Hun Seo ,  Kwang-Il Park ,  Seung-Jun Bae

    IPC: G06F11/00 ,  G11C7/10 ,  G11C11/4093 ,  G11C11/4096 ,  H03M13/00 ,  G06F11/10

    Abstract: A semiconductor memory device includes a memory cell array, an error correction code (ECC) engine, an input/output (I/O) gating circuit and a control logic circuit. The memory cell array includes bank arrays, each of the bank arrays includes a first sub array and a second sub array, and each of the first sub array and the second sub array includes a normal cell region to store data bits and a parity cell region to store parity bits. The ECC engine generates the parity bits and corrects error bit. The I/O gating circuit is connected between the ECC engine and the memory cell array. The control logic circuit controls the I/O gating circuit to perform column access to the normal cell region according to a multiple of a burst length and to perform column access to the parity cell region according to a non-multiple of the burst length partially.

    Memory systems and methods of operating semiconductor memory devices
    7.
    发明授权
    Memory systems and methods of operating semiconductor memory devices 有权

    公开(公告)号：US10204700B1

    公开(公告)日：2019-02-12

    申请号：US15271600

    申请日：2016-09-21

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Yoon-Na Oh ,  Deok-Gu Yoon ,  Sang-Uhn Cha

    IPC: G11C29/52 ,  G06F11/07

    Abstract: A memory system includes a semiconductor memory device and a test device. The semiconductor memory device includes a memory cell array, an error correction circuit and a test circuit. The test device controls a test of the semiconductor memory device, and the test device includes a first fail address memory and a second fail address memory. The test circuit performs a first test on the memory cell array to selectively record a first test result associated with the first test in the first fail address memory and performs a second test on the memory cell array to record a second test result associated with the second test in the second fail address memory. The test circuit is configured to perform the first test and the second test based on a test pattern data from the test device in a test mode.

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