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公开(公告)号：US11881508B2
公开(公告)日：2024-01-23
申请号：US17843105
申请日：2022-06-17
发明人： Kyungin Choi , Hyunchul Song , Sunjung Kim , Taegon Kim , Seong Hoon Jeong
IPC分类号： H01L29/06 , H01L21/02 , H01L21/3105 , H01L21/3115 , H01L21/762 , H01L21/8238 , H01L27/092 , H10B10/00 , H01L21/308 , H01L29/66 , H01L29/78 , H01L21/8234 , H01L27/088 , H01L29/165 , H01L29/08
CPC分类号： H01L29/0653 , H01L21/02164 , H01L21/02271 , H01L21/3105 , H01L21/31155 , H01L21/76224 , H01L21/823828 , H01L21/823878 , H01L27/0924 , H01L29/0847 , H10B10/12 , H01L21/02208 , H01L21/308 , H01L21/823821 , H01L29/6656 , H01L29/66545
摘要： A semiconductor device includes a substrate including a first active pattern and a second active pattern, a device isolation layer filling a first trench between the first and second active patterns, the device isolation layer including a silicon oxide layer doped with helium, a helium concentration of the device isolation layer being higher than a helium concentration of the first and second active patterns, and a gate electrode crossing the first and second active patterns.
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公开(公告)号：US10056491B2
公开(公告)日：2018-08-21
申请号：US15420512
申请日：2017-01-31
发明人： Seong Hoon Jeong , Hong Bum Park , HanMei Choi , Jae Young Park , Seung Hyun Lim
IPC分类号： H01L29/78 , H01L29/06 , H01L29/40 , H01L29/51 , H01L29/66 , H01L29/41 , H01L27/08 , H01L27/10 , H01L21/28 , H01L21/8234 , H01L27/088 , H01L29/423
CPC分类号： H01L29/7854 , H01L21/28158 , H01L21/823431 , H01L21/823462 , H01L27/0886 , H01L29/0657 , H01L29/408 , H01L29/42364 , H01L29/513 , H01L29/66818 , H01L29/7851 , H01L29/7853
摘要： A semiconductor device is provided including a fin active region on a substrate. The fin active region includes a lower region, a middle region, and an upper region. The middle region has lateral surfaces with a slope less steep than the lateral surfaces of the upper region. An isolation region is on a lateral surface of the lower region of the fin active region. A gate electrode structure is provided. A gate dielectric structure having an oxidation oxide layer and a deposition oxide layer, while having a thickness greater than half a width of the upper region of the fin active region is provided. The deposition oxide layer is between the gate electrode structure and the fin active region and the gate electrode structure and the isolation region, and the oxidation oxide layer is between the fin active region and the deposition oxide layer.
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公开(公告)号：US09373703B2
公开(公告)日：2016-06-21
申请号：US14499922
申请日：2014-09-29
发明人： JinBum Kim , Jungho Yoo , Byeongchan Lee , Choeun Lee , Hyun Jung Lee , Seong Hoon Jeong , Bonyoung Koo
IPC分类号： H01L29/66 , H01L21/8234 , H01L29/165
CPC分类号： H01L29/66795 , H01L21/823431 , H01L21/823456 , H01L21/823481 , H01L29/165 , H01L29/66545 , H01L29/6656 , H01L29/7848
摘要： A method of manufacturing a semiconductor device includes forming an active pattern protruding from a semiconductor substrate, forming a dummy gate pattern crossing over the active pattern, forming gate spacers on opposite first and second sidewalls of the dummy gate pattern, removing the dummy gate pattern to form a gate region exposing an upper surface and sidewalls of the active pattern between the gate spacers, recessing the upper surface of the active pattern exposed by the gate region to form a channel recess region, forming a channel pattern in the channel recess region by a selective epitaxial growth (SEG) process, and sequentially forming a gate dielectric layer and a gate electrode covering an upper surface and sidewalls of the channel pattern in the gate region. The channel pattern has a lattice constant different from that of the semiconductor substrate.
摘要翻译： 一种制造半导体器件的方法包括形成从半导体衬底突出的有源图案，形成与有源图案交叉的伪栅极图案，在伪栅极图案的相对的第一和第二侧壁上形成栅极间隔物，将伪栅极图案去除 形成栅极区域，暴露栅极间隔件之间的有源图案的上表面和侧壁，凹陷由栅极区域暴露的有源图案的上表面，以形成通道凹槽区域，在通道凹槽区域中形成通道图案 选择性外延生长（SEG）工艺，以及顺序地形成覆盖栅极区域中的沟道图案的上表面和侧壁的栅极电介质层和栅电极。 沟道图案具有与半导体衬底不同的晶格常数。
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公开(公告)号：US10019349B2
公开(公告)日：2018-07-10
申请号：US14715683
申请日：2015-05-19
发明人： Seong Hoon Jeong , Woong Seo , Sang Heon Lee , Sun Min Kwon , Ho Young Kim , Hee Jun Shim
IPC分类号： G06F12/00 , G06F12/02 , G06F12/06 , G06F12/0846
CPC分类号： G06F12/0207 , G06F12/0607 , G06F12/0846 , G06F2212/1016 , G06F2212/1056 , G06F2212/455
摘要： A cache memory and a method of managing the same are provided. The method of managing a cache memory includes determining whether a number of bits of a data bandwidth stored in a bank is an integer multiple of a number of bits of unit data in data to be stored, storing first unit data, among the data to be stored, in a first region of a first address in the bank in response to the number of bits of the data bandwidth not being the integer multiple of the number of bits of the unit data, and storing part of second unit data, among the data to be stored, in a second region of the first address.
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公开(公告)号：US09710933B2
公开(公告)日：2017-07-18
申请号：US14815077
申请日：2015-07-31
发明人： Hee Jun Shim , Soo Jung Ryu , Sang Heon Lee , Sun Min Kwon , Ho Young Kim , Seong Hoon Jeong
IPC分类号： G06T11/00
CPC分类号： G06T11/001
摘要： Provided is a method of processing a texture. The method includes acquiring texture position information in a texture image corresponding to pixel position information of pixels constituting a frame, acquiring texture classification information (TCI) representing a similarity between respective texture factors of two or more classified regions in the texture image based on the texture position information, determining an amount of texture data requested from a memory according to the TCI, and reading texture data corresponding to the determined amount of texture data based on the texture position information.
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6.发明授权Methods of selectively growing source/drain regions of fin field effect transistor and method of manufacturing semiconductor device including a fin field effect transistor 有权选择性地增长鳍状场效应晶体管的源极/漏极区域的方法及制造包括鳍状场效应晶体管的半导体器件的方法公开(公告)号：US09252244B2
公开(公告)日：2016-02-02
申请号：US14498996
申请日：2014-09-26
发明人： JinBum Kim , Seong Hoon Jeong , Jeon Il Lee , Seokhoon Kim , Kwan Heum Lee , Choeun Lee , Yu-Jin Pyo
IPC分类号： H01L21/336 , H01L29/66 , H01L29/51 , H01L29/161 , H01L21/02 , H01L29/78 , H01L21/8238 , H01L21/8234 , H01L27/12
CPC分类号： H01L29/66795 , H01L21/0223 , H01L21/02252 , H01L21/02326 , H01L21/0234 , H01L21/823418 , H01L21/823431 , H01L21/823821 , H01L27/1211 , H01L29/161 , H01L29/517 , H01L29/66545 , H01L29/6656 , H01L29/785
摘要： The inventive concepts provide methods of manufacturing a semiconductor device. The method includes patterning a substrate to form an active pattern, forming a gate pattern intersecting the active pattern, forming a gate spacer on a sidewall of the gate pattern, forming a growth-inhibiting layer covering an upper region of the gate pattern, and forming source/drain electrodes at opposite first and second sides of the gate pattern.
摘要翻译： 本发明构思提供制造半导体器件的方法。 该方法包括图案化衬底以形成有源图案，形成与有源图案相交的栅极图案，在栅极图案的侧壁上形成栅极间隔物，形成覆盖栅极图案的上部区域的生长抑制层，以及形成 源极/漏极在栅极图案的相对的第一和第二侧。
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公开(公告)号：US20130146830A1
公开(公告)日：2013-06-13
申请号：US13668489
申请日：2012-11-05
发明人： JaeJong Han , Sungun Kwon , Jinhye Bae , Kongsoo Lee , Seong Hoon Jeong , Yoongoo Kang , Hy-Kyun An
CPC分类号： H01L45/1233 , H01L27/1021 , H01L27/2409 , H01L27/2445 , H01L45/06 , H01L45/141
摘要： Semiconductor devices include lower interconnections, upper interconnections crossing over the lower interconnections, selection components disposed at crossing points of the lower interconnections and the upper interconnections, respectively, and memory components disposed between the selection components and the upper interconnections. Each of the selection components may include a semiconductor pattern having a first sidewall and a second sidewall. The first sidewall of the semiconductor pattern may have a first upper width and a first lower width that is greater than the first upper width. The second sidewall of the semiconductor pattern may have a second upper width and a second lower width that is substantially equal to the second upper width.
摘要翻译： 半导体器件包括下互连，在下互连上交叉的上互连，分别设置在下互连和上互连的交叉点处的选择部件以及设置在选择部件和上互连之间的存储器部件。 每个选择部件可以包括具有第一侧壁和第二侧壁的半导体图案。 半导体图案的第一侧壁可以具有大于第一上部宽度的第一上部宽度和第一下部宽度。 半导体图案的第二侧壁可以具有基本上等于第二上部宽度的第二上部宽度和第二下部宽度。
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公开(公告)号：US11380760B2
公开(公告)日：2022-07-05
申请号：US17028042
申请日：2020-09-22
发明人： Kyungin Choi , Hyunchul Song , Sunjung Kim , Taegon Kim , Seong Hoon Jeong
IPC分类号： H01L29/06 , H01L21/02 , H01L21/3105 , H01L21/3115 , H01L21/762 , H01L21/8238 , H01L27/092 , H01L27/11 , H01L29/08 , H01L21/308 , H01L29/66 , H01L27/088 , H01L21/8234 , H01L29/165 , H01L29/78 , H01L29/423
摘要： A semiconductor device includes a substrate including a first active pattern and a second active pattern, a device isolation layer filling a first trench between the first and second active patterns, the device isolation layer including a silicon oxide layer doped with helium, a helium concentration of the device isolation layer being higher than a helium concentration of the first and second active patterns, and a gate electrode crossing the first and second active patterns.
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9.发明授权Semiconductor memory devices having lower and upper interconnections, selection components and memory components 有权半导体存储器件具有下部和上部互连，选择部件和存储器部件公开(公告)号：US08853660B2
公开(公告)日：2014-10-07
申请号：US13668489
申请日：2012-11-05
发明人： JaeJong Han , Sungun Kwon , Jinhye Bae , Kongsoo Lee , Seong Hoon Jeong , Yoongoo Kang , Ho-Kyun An
IPC分类号： H01L29/02
CPC分类号： H01L45/1233 , H01L27/1021 , H01L27/2409 , H01L27/2445 , H01L45/06 , H01L45/141
摘要： Semiconductor devices include lower interconnections, upper interconnections crossing over the lower interconnections, selection components disposed at crossing points of the lower interconnections and the upper interconnections, respectively, and memory components disposed between the selection components and the upper interconnections. Each of the selection components may include a semiconductor pattern having a first sidewall and a second sidewall. The first sidewall of the semiconductor pattern may have a first upper width and a first lower width that is greater than the first upper width. The second sidewall of the semiconductor pattern may have a second upper width and a second lower width that is substantially equal to the second upper width.
摘要翻译： 半导体器件包括下互连，在下互连上交叉的上互连，分别设置在下互连和上互连的交叉点处的选择部件以及设置在选择部件和上互连之间的存储器部件。 每个选择部件可以包括具有第一侧壁和第二侧壁的半导体图案。 半导体图案的第一侧壁可以具有大于第一上部宽度的第一上部宽度和第一下部宽度。 半导体图案的第二侧壁可以具有基本上等于第二上部宽度的第二上部宽度和第二下部宽度。
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