利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

7 条记录 (耗时 0.022 秒)

    Semiconductor Devices Having Shallow Junctions
    4.
    发明申请
    Semiconductor Devices Having Shallow Junctions 审中-公开
    具有浅接头的半导体器件

    公开(公告)号：US20140287564A1

    公开(公告)日：2014-09-25

    申请号：US14287546

    申请日：2014-05-27

    申请人： Samsung Electronics Co., Ltd.

    发明人： Keum-Seok Park ,  Seung-Hun Lee ,  Byeong-Chan Lee ,  Sang-Bom Kang ,  Hong-Bum Park

    IPC分类号： H01L29/66 ,  H01L29/08

    CPC分类号： H01L29/66621 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7848

    摘要： Semiconductor devices are provided including a substrate having a first surface and a second surface recessed from opposite sides of the first surface, a gate pattern formed on the first surface and having a gate insulating layer and a gate electrode, a carbon-doped silicon buffer layer formed on the second surface, and source and drain regions doped with an n-type dopant or p-type dopant, epitaxially grown on the silicon buffer layer to be elevated from a top surface of the gate insulating layer.

    摘要翻译： 提供了半导体器件，其包括具有从第一表面的相对侧凹入的第一表面和第二表面的衬底，形成在第一表面上并具有栅极绝缘层和栅电极的栅极图案，碳掺杂硅缓冲层 形成在第二表面上，以及掺杂有n型掺杂剂或p型掺杂剂的源极和漏极区，其外延生长在硅缓冲层上以从栅极绝缘层的顶表面升高。

    MEMORY DEVICE, STORAGE MODULE, HOST AND OPERATING METHODS THEREOF
    6.
    发明申请
    MEMORY DEVICE, STORAGE MODULE, HOST AND OPERATING METHODS THEREOF 有权

    公开(公告)号：US20220147277A1

    公开(公告)日：2022-05-12

    申请号：US17359841

    申请日：2021-06-28

    申请人： SAMSUNG ELECTRONICS CO., LTD.

    发明人： Doo Hwan Oh ,  Seung-Hun Lee ,  Jin Hun Jeong ,  Chang Ho Yun ,  Kyung-Hee Han

    IPC分类号： G06F3/06

    摘要： Provided is an operating method of a storage device. The method includes providing temperature information of each of a plurality of volatile memory devices in the storage device to a host device; and receiving a setting command related to a refresh operation of the plurality of volatile memory devices from the host device, wherein the plurality of volatile memory devices are classified into groups based on temperature information, and wherein the setting command indicates a number of rows of the plurality of volatile memory devices to be refreshed differently for each of the groups based on the temperature information.

    Memory device including power-up control circuit, and memory system having the same
    7.
    发明授权
    Memory device including power-up control circuit, and memory system having the same 有权
    包括上电控制电路的存储器件和具有相同功能的存储器系统

    公开(公告)号：US09455018B2

    公开(公告)日：2016-09-27

    申请号：US14837294

    申请日：2015-08-27

    申请人： Samsung Electronics Co., Ltd.

    发明人： Seung-Hun Lee ,  Hyung-Chan Choi ,  Won-Jae Shin

    IPC分类号： G11C11/4074 ,  G11C11/408

    CPC分类号： G11C11/4074 ,  G11C5/145 ,  G11C5/148 ,  G11C7/20 ,  G11C8/12 ,  G11C11/4072 ,  G11C11/4087

    摘要： A memory device may include a power-up control circuit and a first set of boost voltage generators. The power-up control circuit may be configured to consecutively activate a first set of power-up signals with a first delay time between each power-up signal of the first set of power-up signals in response to a rise of a power supply voltage and a reset signal having a first logic level at an initial stage of power-up. The first set of boost voltage generators may be configured to generate an internal boost voltage based on an external boost voltage and the first set of power-up signals. The first set of boost voltage generators may be configured to activate before the reset signal transitions from the first logic level to a second logic level opposite to the first logic level.

    摘要翻译： 存储器件可以包括上电控制电路和第一组升压电压发生器。 上电控制电路可以被配置为响应于电源电压的上升，以第一组加电信号的每个上电信号之间的第一延迟时间连续激活第一组上电信号 以及在上电初始阶段具有第一逻辑电平的复位信号。 第一组升压电压发生器可以被配置为基于外部升压电压和第一组上电信号产生内部升压电压。 第一组升压电压发生器可以被配置为在复位信号从第一逻辑电平转变到与第一逻辑电平相反的第二逻辑电平之前激活。