公开(公告)号：US20240324184A1

公开(公告)日：2024-09-26

申请号：US18504226

申请日：2023-11-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seokjae Won ,  Yoongoo Kang ,  Jaehong Park

IPC: H10B12/00

CPC classification number: H10B12/482 ,  H10B12/02 ,  H10B12/315

Abstract: A semiconductor device may include a device isolation part on a substrate, the device isolation part defining a first active portion and a second active portion, with a center portion of the first active portion adjacent in a first direction to an edge portion of the second active portion, A first impurity region may be in the center portion of the first active portion, and a second impurity region may be in the edge portion of the second active portion. A first bit line may be in direct contact with the first impurity region and may extend across the substrate in a second direction that intersects the first direction. A storage node contact may be in contact with the second impurity region, with an upper sidewall and a lower sidewall of the storage node contact on a common side of the storage node contact not vertically aligned with each other.

公开(公告)号：US20240306375A1

公开(公告)日：2024-09-12

申请号：US18444390

申请日：2024-02-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Suyoun Song ,  Yoongoo Kang ,  Kyungwook Park ,  Youmin Ban ,  Changwoo Seo ,  Hyunchul Shim

IPC: H10B12/00

CPC classification number: H10B12/482 ,  H10B12/02

Abstract: An integrated circuit device includes a substrate having a plurality of active regions, a bit line extending in a horizontal direction on the substrate, an insulating capping pattern formed on the bit line and extending along the bit line, a direct contact disposed in a direct contact hole formed on the substrate and connected between a first active region selected from among the plurality of active regions and the bit line, and a spacer structure contacting a sidewall of the direct contact and a sidewall of the bit line The spacer structure includes a first spacer layer extending in a vertical direction on the sidewall of the direct contact and the sidewall of the bit line, and a second spacer layer covering at least a portion of the first spacer layer and extending in the vertical direction.

公开(公告)号：US20230292491A1

公开(公告)日：2023-09-14

申请号：US18090043

申请日：2022-12-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyungwook Park ,  Sangmin Kang ,  Yoongoo Kang ,  Changwoo Seo ,  Suyoun Song ,  Dain Lee

IPC: H10B12/00

CPC classification number: H10B12/315 ,  H10B12/34 ,  H10B12/482 ,  H10B12/0335

Abstract: A semiconductor device may include contact plug structures on a substrate, and an insulation structure filling a space between the contact plug structures to insulate the contact plug structures from each other. The contact plug structures may be spaced apart from each other in a first direction. The insulation structure may include a first insulation pattern and a second insulation pattern. The second insulation pattern may include an insulation material having an etch selectivity with respect to silicon oxide. The first insulation pattern may contact a portion of sidewalls of the second insulation pattern and a portion of sidewalls of the contact plug structure. The first insulation pattern may include a material having a band gap higher than a band gap of the second insulation pattern.

公开(公告)号：US11177215B2

公开(公告)日：2021-11-16

申请号：US16802676

申请日：2020-02-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyungwook Park ,  Yoongoo Kang ,  Wonseok Yoo ,  Dain Lee

IPC: H01L23/532 ,  H01L27/108

Abstract: An integrated circuit device includes a conductive line formed on a substrate, an insulating spacer covering side walls of the conductive line and extending parallel with the conductive line, and a conductive plug that is spaced apart from the conductive line with the insulating spacer therebetween. The insulating spacer includes an insulating liner contacting the conductive line, an outer spacer contacting the conductive plug, and a barrier layer between the insulating liner and the outer spacer to prevent oxygen atoms from diffusing into the outer spacer.

公开(公告)号：US20240334684A1

公开(公告)日：2024-10-03

申请号：US18536334

申请日：2023-12-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dongyoung Kim ,  Yoongoo Kang ,  Jaehong Park

IPC: H10B12/00

CPC classification number: H10B12/485 ,  H10B12/482

Abstract: A semiconductor memory device includes an active pattern on a substrate and at least partially surrounded by a device isolation pattern, a bit line that extends on a center portion of the active pattern in a first direction that is parallel to a bottom surface of the substrate, and a bit line contact between the bit line and the active pattern. The bit line contact includes a metallic material. A width of the bit line contact at a first level and in a second direction is greater than a width of a bottom surface of the bit line contact in the second direction. The second direction intersects the first direction. The first level is between a top surface of the device isolation pattern and the substrate.

公开(公告)号：US20130146830A1

公开(公告)日：2013-06-13

申请号：US13668489

申请日：2012-11-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： JaeJong Han ,  Sungun Kwon ,  Jinhye Bae ,  Kongsoo Lee ,  Seong Hoon Jeong ,  Yoongoo Kang ,  Hy-Kyun An

IPC: H01L45/00 ,  H01L29/82 ,  H01L29/06

CPC classification number: H01L45/1233 ,  H01L27/1021 ,  H01L27/2409 ,  H01L27/2445 ,  H01L45/06 ,  H01L45/141

Abstract: Semiconductor devices include lower interconnections, upper interconnections crossing over the lower interconnections, selection components disposed at crossing points of the lower interconnections and the upper interconnections, respectively, and memory components disposed between the selection components and the upper interconnections. Each of the selection components may include a semiconductor pattern having a first sidewall and a second sidewall. The first sidewall of the semiconductor pattern may have a first upper width and a first lower width that is greater than the first upper width. The second sidewall of the semiconductor pattern may have a second upper width and a second lower width that is substantially equal to the second upper width.

Abstract translation: 半导体器件包括下互连，在下互连上交叉的上互连，分别设置在下互连和上互连的交叉点处的选择部件以及设置在选择部件和上互连之间的存储器部件。 每个选择部件可以包括具有第一侧壁和第二侧壁的半导体图案。 半导体图案的第一侧壁可以具有大于第一上部宽度的第一上部宽度和第一下部宽度。 半导体图案的第二侧壁可以具有基本上等于第二上部宽度的第二上部宽度和第二下部宽度。

公开(公告)号：US20230354587A1

公开(公告)日：2023-11-02

申请号：US18304930

申请日：2023-04-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yoongoo Kang ,  Sangyoon Oh ,  Wonseok Yoo ,  Kyeongock Chong ,  Haeseul Kang

IPC: H10B12/00

CPC classification number: H10B12/482 ,  H10B12/315 ,  H10B12/34 ,  H10B12/02

Abstract: A semiconductor device includes an active region; an isolation region on a side surface of the active region; a gate trench intersecting the active region and extending into the isolation region; a gate structure in the gate trench; a first impurity region and a second impurity region in the active region on both sides of the gate structure and spaced apart from each other; a bit line structure including a line portion intersecting the gate structure and a plug portion below the line portion and electrically connected to the first impurity region; and an insulating structure on a side surface of the plug portion. The insulating structure includes a spacer including a first material; an insulating pattern between the plug portion and the spacer and including a second material; and an insulating liner covering a side surface and a bottom surface of the insulating pattern and including a third material.

公开(公告)号：US11729966B2

公开(公告)日：2023-08-15

申请号：US17723218

申请日：2022-04-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yoongoo Kang ,  Wonseok Yoo ,  Hokyun An ,  Kyungwook Park ,  Dain Lee

IPC: H10B12/00 ,  G11C5/06 ,  H01L29/06

CPC classification number: H10B12/315 ,  G11C5/063 ,  H01L29/0649 ,  H10B12/0335 ,  H10B12/05 ,  H10B12/482

Abstract: A DRAM device includes an isolation region defining source and drain regions in a substrate, a first bit line structure connected to the source region, a second bit line structure disposed on the isolation region, an inner spacer vertically extending on a first sidewall of the first bit line structure, an air gap is between the inner spacer and an outer spacer, a storage contact between the first and second bit line structures and connected to the drain region, a landing pad structure vertically on the storage contact, and a storage structure vertically on the landing pad structure. The sealing layer seals a top of the first air gap. The sealing layer includes a first sealing layer on a first sidewall of a pad isolation trench, and a second sealing layer on a second sidewall of the pad isolation trench and separated from the first sealing layer.

公开(公告)号：US20210066200A1

公开(公告)日：2021-03-04

申请号：US16802676

申请日：2020-02-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyungwook Park ,  Yoongoo Kang ,  Wonseok Yoo ,  Dain Lee

IPC: H01L23/532 ,  H01L27/108

Abstract: An integrated circuit device includes a conductive line formed on a substrate, an insulating spacer covering side walls of the conductive line and extending parallel with the conductive line, and a conductive plug that is spaced apart from the conductive line with the insulating spacer therebetween. The insulating spacer includes an insulating liner contacting the conductive line, an outer spacer contacting the conductive plug, and a barrier layer between the insulating liner and the outer spacer to prevent oxygen atoms from diffusing into the outer spacer.

公开(公告)号：US12230498B2

公开(公告)日：2025-02-18

申请号：US17222195

申请日：2021-04-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dain Lee ,  Yoongoo Kang ,  Wonseok Yoo ,  Jinwon Ma ,  Kyungwook Park ,  Changwoo Seo ,  Suyoun Song

IPC: H01L21/02 ,  C23C16/34 ,  C23C16/36 ,  C23C16/455

Abstract: A semiconductor device manufacturing method includes loading a semiconductor substrate into a chamber, the semiconductor substrate including a silicon oxide film, depositing a seed layer on the silicon oxide film by supplying a first silicon source material, supplying a purge gas on the seed layer, depositing a protective layer on the seed layer by repeating a first cycle, the first cycle including supplying a base source material layer and subsequently supplying the first silicon source material, and depositing a silicon nitride film on the protective layer by repeating a second cycle, the second cycle including supplying a second silicon source material and subsequently supplying a nitrogen source material.