公开(公告)号：US20180239541A1

公开(公告)日：2018-08-23

申请号：US15962706

申请日：2018-04-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Young-Jin Jeon

IPC: G06F3/06 ,  G11C11/4093 ,  G11C11/408 ,  G11C11/4096 ,  G11C11/4076

CPC classification number: G06F3/0614 ,  G06F3/0629 ,  G06F3/0659 ,  G06F3/0673 ,  G11C7/1072 ,  G11C7/22 ,  G11C7/222 ,  G11C8/06 ,  G11C8/18 ,  G11C11/4076 ,  G11C11/4082 ,  G11C11/4087 ,  G11C11/409 ,  G11C11/4093 ,  G11C11/4096 ,  G11C29/023 ,  G11C29/028 ,  G11C2207/2254

Abstract: During a command/address calibration mode, a memory controller may transmit multiple cycles of test patterns as signals to a memory device. Each cycle of test pattern signals may be transmitted at an adjusted relative phase with respect to a clock also transmitted to the memory device. The memory device may input the test pattern signals at a timing determined by the clock, such as rising and/or falling edges of the clock. The test pattern as input by the memory device may be sent to the memory controller to determine if the test pattern was successfully transmitted to the memory device during the cycle. Multiple cycles of test pattern transmissions are evaluated to determine a relative phase of command/address signals with respect to the clock for transmission during operation of the system.

公开(公告)号：US09595314B2

公开(公告)日：2017-03-14

申请号：US15193128

申请日：2016-06-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Young-Jin Jeon

IPC: G11C7/00 ,  G11C11/4076 ,  G11C11/4096 ,  G11C11/408

CPC classification number: G06F3/0614 ,  G06F3/0629 ,  G06F3/0659 ,  G06F3/0673 ,  G11C7/1072 ,  G11C7/22 ,  G11C7/222 ,  G11C8/06 ,  G11C8/18 ,  G11C11/4076 ,  G11C11/4082 ,  G11C11/4087 ,  G11C11/409 ,  G11C11/4093 ,  G11C11/4096 ,  G11C29/023 ,  G11C29/028 ,  G11C2207/2254

Abstract: During a command/address calibration mode, a memory controller may transmit multiple cycles of test patterns as signals to a memory device. Each cycle of test pattern signals may be transmitted at an adjusted relative phase with respect to a clock also transmitted to the memory device. The memory device may input the test pattern signals at a timing determined by the clock, such as rising and/or falling edges of the clock. The test pattern as input by the memory device may be sent to the memory controller to determine if the test pattern was successfully transmitted to the memory device during the cycle. Multiple cycles of test pattern transmissions are evaluated to determine a relative phase of command/address signals with respect to the clock for transmission during operation of the system.

Abstract translation: 在命令/地址校准模式期间，存储器控制器可以将多个测试图案周期作为信号发送到存储器件。 测试模式信号的每个周期可以相对于也传送到存储器件的时钟以调整的相对相位传输。 存储器件可以在由时钟确定的定时（例如时钟的上升沿和/或下降沿）输入测试图形信号。 可以将由存储器件输入的测试图案发送到存储器控制器，以确定在该周期期间测试图案是否被成功发送到存储器件。 评估测试模式传输的多个周期，以确定命令/地址信号相对于系统操作期间传输的时钟的相对相位。

公开(公告)号：US20170139612A1

公开(公告)日：2017-05-18

申请号：US15420350

申请日：2017-01-31

Applicant: Samsung Electronics Co., Ltd.

Inventor： Young-Jin Jeon

IPC: G06F3/06 ,  G11C11/4093 ,  G11C11/408 ,  G11C11/4076 ,  G11C11/4096

CPC classification number: G06F3/0614 ,  G06F3/0629 ,  G06F3/0659 ,  G06F3/0673 ,  G11C7/1072 ,  G11C7/22 ,  G11C7/222 ,  G11C8/06 ,  G11C8/18 ,  G11C11/4076 ,  G11C11/4082 ,  G11C11/4087 ,  G11C11/409 ,  G11C11/4093 ,  G11C11/4096 ,  G11C29/023 ,  G11C29/028 ,  G11C2207/2254

Abstract: During a command/address calibration mode, a memory controller may transmit multiple cycles of test patterns as signals to a memory device. Each cycle of test pattern signals may be transmitted at an adjusted relative phase with respect to a clock also transmitted to the memory device. The memory device may input the test pattern signals at a timing determined by the clock, such as rising and/or falling edges of the clock. The test pattern as input by the memory device may be sent to the memory controller to determine if the test pattern was successfully transmitted to the memory device during the cycle. Multiple cycles of test pattern transmissions are evaluated to determine a relative phase of command/address signals with respect to the clock for transmission during operation of the system.

公开(公告)号：US08879342B2

公开(公告)日：2014-11-04

申请号：US14295320

申请日：2014-06-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Young-Jin Jeon

IPC: G11C7/00 ,  G11C8/06 ,  G11C8/18 ,  G11C7/22 ,  G11C7/10

CPC classification number: G06F3/0614 ,  G06F3/0629 ,  G06F3/0659 ,  G06F3/0673 ,  G11C7/1072 ,  G11C7/22 ,  G11C7/222 ,  G11C8/06 ,  G11C8/18 ,  G11C11/4076 ,  G11C11/4082 ,  G11C11/4087 ,  G11C11/409 ,  G11C11/4093 ,  G11C11/4096 ,  G11C29/023 ,  G11C29/028 ,  G11C2207/2254

Abstract: During a command/address calibration mode, a memory controller may transmit multiple cycles of test patterns as signals to a memory device. Each cycle of test pattern signals may be transmitted at an adjusted relative phase with respect to a clock also transmitted to the memory device. The memory device may input the test pattern signals at a timing determined by the clock, such as rising and/or falling edges of the clock. The test pattern as input by the memory device may be sent to the memory controller to determine if the test pattern was successfully transmitted to the memory device during the cycle. Multiple cycles of test pattern transmissions are evaluated to determine a relative phase of command/address signals with respect to the clock for transmission during operation of the system.

Abstract translation: 在命令/地址校准模式期间，存储器控制器可以将多个测试图案周期作为信号发送到存储器件。 测试模式信号的每个周期可以相对于也传送到存储器件的时钟以调整的相对相位传输。 存储器件可以在由时钟确定的定时（例如时钟的上升沿和/或下降沿）输入测试图形信号。 可以将由存储器件输入的测试图案发送到存储器控制器，以确定在该周期期间测试图案是否被成功发送到存储器件。 评估测试模式传输的多个周期，以确定命令/地址信号相对于系统操作期间传输的时钟的相对相位。

公开(公告)号：US09971521B2

公开(公告)日：2018-05-15

申请号：US15667130

申请日：2017-08-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Young-Jin Jeon

IPC: G11C7/00 ,  G06F3/06 ,  G11C11/408 ,  G11C11/4093 ,  G11C11/4096 ,  G11C11/4076

CPC classification number: G06F3/0614 ,  G06F3/0629 ,  G06F3/0659 ,  G06F3/0673 ,  G11C7/1072 ,  G11C7/22 ,  G11C7/222 ,  G11C8/06 ,  G11C8/18 ,  G11C11/4076 ,  G11C11/4082 ,  G11C11/4087 ,  G11C11/409 ,  G11C11/4093 ,  G11C11/4096 ,  G11C29/023 ,  G11C29/028 ,  G11C2207/2254

Abstract: During a command/address calibration mode, a memory controller may transmit multiple cycles of test patterns as signals to a memory device. Each cycle of test pattern signals may be transmitted at an adjusted relative phase with respect to a clock also transmitted to the memory device. The memory device may input the test pattern signals at a timing determined by the clock, such as rising and/or falling edges of the clock. The test pattern as input by the memory device may be sent to the memory controller to determine if the test pattern was successfully transmitted to the memory device during the cycle. Multiple cycles of test pattern transmissions are evaluated to determine a relative phase of command/address signals with respect to the clock for transmission during operation of the system.

公开(公告)号：US09401197B2

公开(公告)日：2016-07-26

申请号：US14729058

申请日：2015-06-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Young-Jin Jeon

IPC: G11C7/00 ,  G11C11/4076 ,  G11C8/18 ,  G11C29/02 ,  G11C7/10 ,  G11C7/22 ,  G11C8/06 ,  G11C11/408 ,  G11C11/409

CPC classification number: G06F3/0614 ,  G06F3/0629 ,  G06F3/0659 ,  G06F3/0673 ,  G11C7/1072 ,  G11C7/22 ,  G11C7/222 ,  G11C8/06 ,  G11C8/18 ,  G11C11/4076 ,  G11C11/4082 ,  G11C11/4087 ,  G11C11/409 ,  G11C11/4093 ,  G11C11/4096 ,  G11C29/023 ,  G11C29/028 ,  G11C2207/2254

Abstract: During a command/address calibration mode, a memory controller may transmit multiple cycles of test patterns as signals to a memory device. Each cycle of test pattern signals may be transmitted at an adjusted relative phase with respect to a clock also transmitted to the memory device. The memory device may input the test pattern signals at a timing determined by the clock, such as rising and/or falling edges of the clock. The test pattern as input by the memory device may be sent to the memory controller to determine if the test pattern was successfully transmitted to the memory device during the cycle. Multiple cycles of test pattern transmissions are evaluated to determine a relative phase of command/address signals with respect to the clock for transmission during operation of the system.

公开(公告)号：US20150262649A1

公开(公告)日：2015-09-17

申请号：US14729058

申请日：2015-06-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Young-Jin Jeon

IPC: G11C11/4076 ,  G11C11/409 ,  G11C11/408

CPC classification number: G06F3/0614 ,  G06F3/0629 ,  G06F3/0659 ,  G06F3/0673 ,  G11C7/1072 ,  G11C7/22 ,  G11C7/222 ,  G11C8/06 ,  G11C8/18 ,  G11C11/4076 ,  G11C11/4082 ,  G11C11/4087 ,  G11C11/409 ,  G11C11/4093 ,  G11C11/4096 ,  G11C29/023 ,  G11C29/028 ,  G11C2207/2254

Abstract: During a command/address calibration mode, a memory controller may transmit multiple cycles of test patterns as signals to a memory device. Each cycle of test pattern signals may be transmitted at an adjusted relative phase with respect to a clock also transmitted to the memory device. The memory device may input the test pattern signals at a timing determined by the clock, such as rising and/or falling edges of the clock. The test pattern as input by the memory device may be sent to the memory controller to determine if the test pattern was successfully transmitted to the memory device during the cycle. Multiple cycles of test pattern transmissions are evaluated to determine a relative phase of command/address signals with respect to the clock for transmission during operation of the system.

Abstract translation: 在命令/地址校准模式期间，存储器控制器可以将多个测试图案周期作为信号发送到存储器件。 测试模式信号的每个周期可以相对于也传送到存储器件的时钟以调整的相对相位传输。 存储器件可以在由时钟确定的定时（例如时钟的上升沿和/或下降沿）输入测试图形信号。 可以将由存储器件输入的测试图案发送到存储器控制器，以确定在该周期期间测试图案是否被成功发送到存储器件。 评估测试模式传输的多个周期，以确定命令/地址信号相对于系统操作期间传输的时钟的相对相位。

公开(公告)号：US09030262B2

公开(公告)日：2015-05-12

申请号：US13834132

申请日：2013-03-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Young-Chul Cho ,  Yoon-Joo Eom ,  Young-Jin Jeon ,  Yong-Cheol Bae

IPC: H03F3/04 ,  H03F3/45 ,  G11C5/00

CPC classification number: H03F3/45076 ,  G11C5/00 ,  G11C7/1084 ,  H03F3/45183 ,  H03F2200/372 ,  H03F2203/45702

Abstract: An input receiver circuit including a single-to-differential amplifier and a semiconductor device including the input receiver circuit are disclosed. The input receiver circuit includes a first stage amplifier unit and a second stage amplifier unit. The first stage amplifier unit amplifies a single input signal in a single-to-differential mode to generate a differential output signal, without using a reference voltage. The second stage amplifier unit amplifies the differential output signal in a differential-to-single mode to generate a single output signal.

Abstract translation: 公开了包括单差分放大器和包括输入接收器电路的半导体器件的输入接收器电路。 输入接收机电路包括第一级放大器单元和第二级放大器单元。 第一级放大器单元以单差模式放大单个输入信号以产生差分输出信号，而不使用参考电压。 第二级放大器单元以差分到单个模式放大差分输出信号以产生单个输出信号。

公开(公告)号：US20150016202A1

公开(公告)日：2015-01-15

申请号：US14504087

申请日：2014-10-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Young-Jin Jeon

IPC: G11C7/22 ,  G11C8/18

CPC classification number: G06F3/0614 ,  G06F3/0629 ,  G06F3/0659 ,  G06F3/0673 ,  G11C7/1072 ,  G11C7/22 ,  G11C7/222 ,  G11C8/06 ,  G11C8/18 ,  G11C11/4076 ,  G11C11/4082 ,  G11C11/4087 ,  G11C11/409 ,  G11C11/4093 ,  G11C11/4096 ,  G11C29/023 ,  G11C29/028 ,  G11C2207/2254

Abstract: During a command/address calibration mode, a memory controller may transmit multiple cycles of test patterns as signals to a memory device. Each cycle of test pattern signals may be transmitted at an adjusted relative phase with respect to a clock also transmitted to the memory device. The memory device may input the test pattern signals at a timing determined by the clock, such as rising and/or falling edges of the clock. The test pattern as input by the memory device may be sent to the memory controller to determine if the test pattern was successfully transmitted to the memory device during the cycle. Multiple cycles of test pattern transmissions are evaluated to determine a relative phase of command/address signals with respect to the clock for transmission during operation of the system.

公开(公告)号：US20140286119A1

公开(公告)日：2014-09-25

申请号：US14295320

申请日：2014-06-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Young-Jin Jeon

IPC: G11C8/06 ,  G11C8/18

CPC classification number: G06F3/0614 ,  G06F3/0629 ,  G06F3/0659 ,  G06F3/0673 ,  G11C7/1072 ,  G11C7/22 ,  G11C7/222 ,  G11C8/06 ,  G11C8/18 ,  G11C11/4076 ,  G11C11/4082 ,  G11C11/4087 ,  G11C11/409 ,  G11C11/4093 ,  G11C11/4096 ,  G11C29/023 ,  G11C29/028 ,  G11C2207/2254

Abstract: During a command/address calibration mode, a memory controller may transmit multiple cycles of test patterns as signals to a memory device. Each cycle of test pattern signals may be transmitted at an adjusted relative phase with respect to a clock also transmitted to the memory device. The memory device may input the test pattern signals at a timing determined by the clock, such as rising and/or falling edges of the clock. The test pattern as input by the memory device may be sent to the memory controller to determine if the test pattern was successfully transmitted to the memory device during the cycle. Multiple cycles of test pattern transmissions are evaluated to determine a relative phase of command/address signals with respect to the clock for transmission during operation of the system.

Abstract translation: 在命令/地址校准模式期间，存储器控制器可以将多个测试图案周期作为信号发送到存储器件。 测试模式信号的每个周期可以相对于也传送到存储器件的时钟以调整的相对相位传输。 存储器件可以在由时钟确定的定时（例如时钟的上升沿和/或下降沿）输入测试图形信号。 可以将由存储器件输入的测试图案发送到存储器控制器，以确定在该周期期间测试图案是否被成功发送到存储器件。 评估测试模式传输的多个周期，以确定命令/地址信号相对于系统操作期间传输的时钟的相对相位。