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公开(公告)号：US12205951B2
公开(公告)日：2025-01-21
申请号：US17491841
申请日：2021-10-01
Applicant: Samsung Electronics Co., Ltd.
Inventor： Sangwook Kim , Seunggeol Nam , Taehwan Moon , Kwanghee Lee , Jinseong Heo , Hagyoul Bae , Yunseong Lee
IPC: H01L27/092 , H01L29/24 , H01L29/51 , H01L29/78 , H01L29/786 , H10B10/00
Abstract: Provided is a semiconductor device including a first semiconductor transistor including a semiconductor channel layer, and a metal-oxide semiconductor channel layer, and having a structure in which a second semiconductor transistor is stacked on the top of the first semiconductor transistor. A gate stack of the second semiconductor transistor and the top of a gate stack of the first semiconductor transistor may overlap by greater than or equal to 90%. The first semiconductor transistor and the second semiconductor transistor may have a similar level of operation characteristics.
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公开(公告)号：US11527646B2
公开(公告)日：2022-12-13
申请号：US17026665
申请日：2020-09-21
Applicant: Samsung Electronics Co., Ltd.
Inventor： Jinseong Heo , Sangwook Kim , Yunseong Lee , Sanghyun Jo
Abstract: A domain switching device includes a channel region, a source region and a drain region connected to the channel region, a gate electrode isolated from contact with the channel region, an anti-ferroelectric layer between the channel region and the gate electrode, a conductive layer between the gate electrode and the anti-ferroelectric layer to contact the anti-ferroelectric layer, and a barrier layer between the anti-ferroelectric layer and the channel region.
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公开(公告)号：US11417763B2
公开(公告)日：2022-08-16
申请号：US16682512
申请日：2019-11-13
Applicant: Samsung Electronics Co., Ltd.
Inventor： Sangwook Kim , Yunseong Lee , Sanghyun Jo , Jinseong Heo
IPC: H01L29/78 , H01L27/088 , H01L29/51 , H01L21/8234 , H01L21/28 , H01L29/66
Abstract: An integrated circuit includes transistors respectively including channel layers in a substrate, source electrodes and drain electrodes respectively contacting both sides of the channel layers, gate electrodes on the channel layers, and ferroelectrics layers between the channel layers and the gate electrodes. Electrical characteristics of the ferroelectrics layers of at least two of the transistors are different. Accordingly, threshold voltages of the transistors are different from each other.
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公开(公告)号：US11177283B2
公开(公告)日：2021-11-16
申请号：US16893888
申请日：2020-06-05
Applicant: Samsung Electronics Co., Ltd.
Inventor： Jinseong Heo , Yunseong Lee , Sanghyun Jo
Abstract: Provided are an electronic device and a method of manufacturing the same. The electronic device may include a first device provided on a first region of a substrate; and a second device provided on a second region of the substrate, wherein the first device may include a first domain layer including a ferroelectric domain and a first gate electrode on the first domain layer, and the second device may include a second domain layer including a ferroelectric domain and a second gate electrode on the second domain layer. The first domain layer and the second domain layer may have different characteristics from each other at a polarization change according to an electric field. At the polarization change according to the electric field, the first domain layer may have substantially a non-hysteretic behavior characteristic and the second domain layer may have a hysteretic behavior characteristic.
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公开(公告)号：US20190033704A1
公开(公告)日：2019-01-31
申请号：US15946087
申请日：2018-04-05
Applicant: Samsung Electronics Co., Ltd.
Inventor： Seongjun JEONG , Hyeonjin Shin , Sangwon Kim , Seongjun Park , Minsu Seol , Dongwook Lee , Yunseong Lee , Alum Jung
CPC classification number: G03F1/62 , G03F1/22 , G03F7/70008 , G03F7/70983
Abstract: A pellicle composition for a photomask, a pellicle for a photomask, the pellicle for a photomask being formed from the pellicle composition, a method of forming the pellicle, a reticle including the pellicle, and an exposure apparatus for lithography including the reticle are provided. The pellicle composition includes: at least one selected from graphene quantum dots and a graphene quantum dot precursor, the graphene quantum dots having a size of about 50 nm or less; and a solvent.
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6.发明授权
公开(公告)号：US09929238B2
公开(公告)日：2018-03-27
申请号：US15494035
申请日：2017-04-21
Applicant: Samsung Electronics Co., Ltd.
Inventor： Seongjun Jeong , Seongjun Park , Yunseong Lee
IPC: H01L29/16 , H01L29/06 , H01L29/786 , H01L27/088 , H01L21/8234 , H01L21/02 , H01L21/04
CPC classification number: H01L29/1606 , B82Y10/00 , B82Y40/00 , H01L21/02527 , H01L21/02603 , H01L21/042 , H01L21/3065 , H01L21/3081 , H01L21/3085 , H01L21/3086 , H01L21/3088 , H01L21/467 , H01L21/823412 , H01L27/088 , H01L29/0665 , H01L29/0673 , H01L29/0676 , H01L29/66037 , H01L29/66045 , H01L29/775 , H01L29/778 , H01L29/78696 , H01L51/0045 , Y10S977/755 , Y10S977/888
Abstract: Methods of forming a graphene nanopattern, graphene-containing devices, and methods of manufacturing the graphene-containing devices are provided. A method of forming the graphene nanopattern may include forming a graphene layer on a substrate, forming a block copolymer layer on the graphene layer and a region of the substrate exposed on at least one side of the graphene layer, forming a mask pattern from the block copolymer layer by removing one of a plurality of first region and a plurality of second regions of the block copolymer, and patterning the graphene layer in a nanoscale by using the mask pattern as an etching mask. The block copolymer layer may be formed to directly contact the graphene layer. The block copolymer layer may be formed to directly contact a region of the substrate structure that is exposed on at least one side of the graphene layer.
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公开(公告)号：US12230711B2
公开(公告)日：2025-02-18
申请号：US18487275
申请日：2023-10-16
Applicant: Samsung Electronics Co., Ltd.
Inventor： Jinseong Heo , Sangwook Kim , Yunseong Lee , Sanghyun Jo , Hyangsook Lee
Abstract: Provided are an electronic device and a method of manufacturing the same. The electronic device includes a ferroelectric crystallization layer between a substrate and a gate electrode and a crystallization prevention layer between the substrate and the ferroelectric crystallization layer. The ferroelectric crystallization layer is at least partially crystallized and includes a dielectric material having ferroelectricity or anti-ferroelectricity. Also, the crystallization prevention layer prevents crystallization in the ferroelectric crystallization layer from being spread toward the substrate.
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公开(公告)号：US12100749B2
公开(公告)日：2024-09-24
申请号：US18059700
申请日：2022-11-29
Applicant: Samsung Electronics Co., Ltd.
Inventor： Yunseong Lee , Sangwook Kim , Sanghyun Jo , Jinseong Heo , Hyangsook Lee
CPC classification number: H01L29/516 , H01L21/0228 , H01L29/78391
Abstract: A ferroelectric thin-film structure includes at least one first atomic layer and at least one second atomic layer. The first atomic layer includes a first dielectric material that is based on an oxide, and the second atomic layer includes both the first dielectric material and a dopant that has a bandgap greater than a bandgap of the dielectric material.
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公开(公告)号：US11887989B2
公开(公告)日：2024-01-30
申请号：US16943161
申请日：2020-07-30
Applicant: Samsung Electronics Co., Ltd.
Inventor： Sangwook Kim , Jinseong Heo , Yunseong Lee , Sanghyun Jo
IPC: H01L29/786 , H01L27/12 , G06N3/08 , G06N3/063
CPC classification number: H01L27/1207 , G06N3/063 , G06N3/08
Abstract: A semiconductor device includes a first transistor including a first channel layer of a first conductivity type, a second transistor provided in parallel with the first transistor and including a second channel layer of a second conductivity type, and a third transistor stacked on the first and second transistors. The third transistor may include a gate insulating film including a ferroelectric material. The third transistor may include third channel layer and a gate electrode that are spaced apart from each other in a thickness direction with the gate insulating film therebetween.
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公开(公告)号：US11862704B2
公开(公告)日：2024-01-02
申请号：US18059660
申请日：2022-11-29
Applicant: Samsung Electronics Co., Ltd.
Inventor： Jinseong Heo , Yunseong Lee , Sanghyun Jo , Keunwook Shin , Hyeonjin Shin
CPC classification number: H01L29/513 , H01L21/0228 , H01L21/02115 , H01L21/02164 , H01L21/02178 , H01L21/02181 , H01L21/02189 , H01L21/02356 , H01L29/516
Abstract: Provided are electronic devices and methods of manufacturing the same. An electronic device may include a substrate, a gate electrode on the substrate, a ferroelectric layer between the substrate and the gate electrode, and a carbon layer between the substrate and the ferroelectric layer. The carbon layer may have an sp2 bonding structure.
